Patent application number | Description | Published |
20080198545 | Open-frame solid-state drive housing with intrinsic grounding to protect exposed chips - An open-frame flash-memory drive has a printed-circuit board assembly (PCBA) with flash-memory chips, a controller chip, and a Serial AT-Attachment (SATA) connector soldered to it. The PCBA is only partially encased by left and right frames or by a U-shaped bracket frame. The frames have PCBA supports and guide posts that fit near edges of the PCBA. The frames do not cover the top and bottom of the PCBA, allowing chips on the PCBA to be ventilated by unblocked air flow. Screws that attach the PCBA to the frame have metal collars that ground the frame to the PCBA's ground plane. The screws form a current path to draw any electro-static-discharge (ESD) current off the frame and onto a PCBA ground. When the SATA connector is inserted into a host, the host ground sinks ESD currents collected by the open frame. | 08-21-2008 |
20080235443 | Intelligent Solid-State Non-Volatile Memory Device (NVMD) System With Multi-Level Caching of Multiple Channels - A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security. | 09-25-2008 |
20080250195 | Multi-Operation Write Aggregator Using a Page Buffer and a Scratch Flash Block in Each of Multiple Channels of a Large Array of Flash Memory to Reduce Block Wear - A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer is reached, the page buffer is written to a target physical block if full, or combined with old data fragments in an Aggregating Flash Block (AFB) when the logical-sector addresses (LSA's) match. Thus small fragments are aggregated using the AFB, reducing erases and wear of flash blocks. The page buffer is copied to the AFB when a STOP command occurs. Each channel has one or more AFB's, which are tracked by an AFB tracking table. | 10-09-2008 |
20080266991 | Synchronous Page-Mode Phase-Change Memory with ECC and RAM Cache - Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks. | 10-30-2008 |
20080320214 | Multi-Level Controller with Smart Storage Transfer Manager for Interleaving Multiple Single-Chip Flash Memory Devices - A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device. | 12-25-2008 |
20090037652 | Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules - A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands. | 02-05-2009 |
20090113121 | Swappable Sets of Partial-Mapping Tables in a Flash-Memory System With A Command Queue for Combining Flash Writes - A flash controller has a flash interface accessing physical blocks of multi-level-cell (MLC) flash memory. An Extended Universal-Serial-Bus (EUSB) interface loads host commands into a command queue where writes are re-ordered and combined to reduce flash writes. A partial logical-to-physical L2P mapping table in a RAM has entries for only 1 of N sets of L2P mapping tables. The other N−1 sets are stored in flash memory and fetched into the RAM when a L2P table miss occurs. The RAM required for mapping is greatly reduced. A data buffer stores one page of host write data. Sector writes are merged using the data buffer. The data buffer is flushed to flash when a different page is written, while the partial logical-to-physical mapping table is flushed to flash when a L2P table miss occurs, when the host address is to a different one of the N sets of L2P mapping tables. | 04-30-2009 |
20090193184 | Hybrid 2-Level Mapping Tables for Hybrid Block- and Page-Mode Flash-Memory System - A hybrid solid-state disk (SSD) has multi-level-cell (MLC) or single-level-cell (SLC) flash memory, or both. SLC flash may be emulated by MLC that uses fewer cell states. A NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Most data is block-mapped and stored in MLC flash, but some critical or high-frequency data is page-mapped to reduce block-relocation copying. A hybrid mapping table has a first-level and a second level. Only the first level is used for block-mapped data, but both levels are used for page-mapped data. The first level contains a block-page bit that indicates if the data is block-mapped or page-mapped. A PBA field in the first-level table maps block-mapped data, while a virtual field points to the second-level table where the PBA and page number is stored for page-mapped data. Page-mapped data is identified by a frequency counter or sector count. SRAM space is reduced. | 07-30-2009 |
20090204872 | Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules - A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands. | 08-13-2009 |
20090240873 | Multi-Level Striping and Truncation Channel-Equalization for Flash-Memory System - Truncation reduces the available striped data capacity of all flash channels to the capacity of the smallest flash channel. A solid-state disk (SSD) has a smart storage switch salvages flash storage removed from the striped data capacity by truncation. Extra storage beyond the striped data capacity is accessed as scattered data that is not striped. The size of the striped data capacity is reduced over time as more bad blocks appear. A first-level striping map stores striped and scattered capacities of all flash channels and maps scattered and striped data. Each flash channel has a Non-Volatile Memory Device (NVMD) with a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory in the NVMD. Wear-leveling and bad block remapping are preformed by each NVMD. Source and shadow flash blocks are recycled by the NVMD. Two levels of smart storage switches enable three-level controllers. | 09-24-2009 |
20100023682 | Flash-Memory System with Enhanced Smart-Storage Switch and Packed Meta-Data Cache for Mitigating Write Amplification by Delaying and Merging Writes until a Host Read - A flash memory solid-state-drive (SSD) has a smart storage switch that reduces write acceleration that occurs when more data is written to flash memory than is received from the host. Page mapping rather than block mapping reduces write acceleration. Host commands are loaded into a Logical-Block-Address (LBA) range FIFO. Entries are sub-divided and portions invalidated when a new command overlaps an older command in the FIFO. Host data is aligned to page boundaries with pre- and post-fetched data filling in to the boundaries. Repeated data patterns are detected and encoded by compressed meta-data codes that are stored in meta-pattern entries in a meta-pattern cache of a meta-pattern flash block. The sector data is not written to flash. The meta-pattern entries are located using a meta-data mapping table. Storing host CRC's for comparison to incoming host data can detect identical data writes that can be skipped, avoiding a write to flash. | 01-28-2010 |
20100027329 | Synchronous Page-Mode Phase-Change Memory with ECC and RAM Cache - Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks. | 02-04-2010 |
20100122021 | USB-Attached-SCSI Flash-Memory System with Additional Command, Status, and Control Pipes to a Smart-Storage Switch - An electronic flash-memory card has additional pipes for commands and status messages so that data pipes are not clogged with commands and status messages, allowing for a higher data throughput. The command and status pipes are activated when a UAS/BOT detector detects that a host is using a USB-Attached-SCSI (UAS) mode rather than a Bulk-Only-Transfer (BOT) mode. The host can send additional commands and data without waiting for completion of a prior command when operating in UAS mode but not while operating in BOT mode. A command queue (CQ) in the device re-orders commands for accessing flash memory and merges data in a RAM buffer. Smaller 1 KB USB packets in the data pipes are merged into larger 8 KB payloads in the RAM buffer, allowing for more efficient flash access. | 05-13-2010 |
20100275037 | Low-Power USB SuperSpeed Device with 8-bit Payload and 9-bit Frame NRZI Encoding for Replacing 8/10-bit Encoding - A Low-power flash-memory device uses a modified Universal-Serial-Bus (USB) 3.0 Protocol to reduce power consumption. The bit clock is slowed to reduce power and the need for pre-emphasis when USB cable lengths are short in applications. Data efficiency is improved by eliminating the 8/10-bit encoder and instead encoding sync and framing bytes as 9-bit symbols. Data bytes are expanded by bit stuffing only when a series of six ones occurs in the data. Header and payload data is transmitted as nearly 8-bits per data byte while framing is 9-bits per symbol, much less than the standard 10 bits per byte. Low-power link layers, physical layers, and scaled-down protocol layers are used. A card reader converter hub allows USB hosts to access low-power USB devices. Only one flash device is accessed, reducing power compared with standard USB broadcasting to multiple devices. | 10-28-2010 |
20110016267 | Low-Power USB Flash Card Reader Using Bulk-Pipe Streaming with UAS Command Re-Ordering and Channel Separation - A flash-card reader improves transmission efficiency by using bulk streaming of multiple pipes. A bulk data-out pipe carries host write data to the card reader and can operate in parallel with a bulk data-in pipe that carries host read data that was read from a flash card attached to the card reader. Status packets do not block data packets since the he status packets are buffered through a separate status pipe, and commands are buffered through a command pipe. Flash data from multiple flash cards are interleaved as separate endpoints that share the bulk data-in pipe. A data in/out streaming state machine controls streaming bulk data through the bulk data-in and data-out pipes, while a status streaming state machine controls streaming status packets through the status pipe. Transaction overhead is reduced using bulk streaming where packets for several commands are combined into the same bulk streams. | 01-20-2011 |
20110066837 | Single-Chip Flash Device with Boot Code Transfer Capability - A Multi-Media Card (MMC) Single-Chip Flash Device (SCFD) contains a MMC flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. An initial boot loader is read from the first page of flash by a state machine and written to a small RAM. A central processing unit (CPU) in the microcontroller reads instructions from the small RAM, executing the initial boot loader, which reads more pages from flash. These pages are buffered by the small RAM and written to a larger DRAM. Once an extended boot sequence is written to DRAM, the CPU toggles a RAM_BASE bit to cause instruction fetching from DRAM. Then the extended boot sequence is executed from DRAM, copying an OS image from flash to DRAM. Boot code and control code are selectively overwritten during a code updating operation to eliminate stocking issues. | 03-17-2011 |
20110213921 | Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules - A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands. | 09-01-2011 |
20110302358 | Flash-Memory Device with RAID-type Controller - A smart flash drive has one or more levels of smart storage switches and a lower level of single-chip flash devices (SCFD's). A SCFD contains flash memory and controllers that perform low-level bad-block mapping and wear-leveling and logical-to-physical block mapping. The SCFD report their capacity, arrangement, and maximum wear-level count (WLC) and bad block number (BBN) to the upstream smart storage switch, which stores this information in a structure register. The smart storage switch selects the SCFD with the maximum BBN as the target and the SCFD with the lowest maximum WLC as the source of a swap for wear leveling when a WLC exceeds a threshold that rises over time. A top-level smart storage switch receives consolidated capacity, arrangement, WLC, and BBN information from lower-level smart storage switch. Data is striped and optionally scrambled by Redundant Array of Individual Disks (RAID) controllers in all levels of smart storage switches. | 12-08-2011 |
20120278543 | Flash-Memory Device with RAID-type Controller - A smart flash drive has one or more levels of smart storage switches and a lower level of single-chip flash devices (SCFD's). A SCFD contains flash memory and controllers that perform low-level bad-block mapping and wear-leveling and logical-to-physical block mapping. The SCFD report their capacity, arrangement, and maximum wear-level count (WLC) and bad block number (BBN) to the upstream smart storage switch, which stores this information in a structure register. The smart storage switch selects the SCFD with the maximum BBN as the target and the SCFD with the lowest maximum WLC as the source of a swap for wear leveling when a WLC exceeds a threshold that rises over time. A top-level smart storage switch receives consolidated capacity, arrangement, WLC, and BBN information from lower-level smart storage switch. Data is striped and optionally scrambled by Redundant Array of Individual Disks (RAID) controllers in all levels of smart storage switches. | 11-01-2012 |
20120284587 | Super-Endurance Solid-State Drive with Endurance Translation Layer (ETL) and Diversion of Temp Files for Reduced Flash Wear - A flash drive has increased endurance and longevity by reducing writes to flash. An Endurance Translation Layer (ETL) is created in a DRAM buffer and provides temporary storage to reduce flash wear. A Smart Storage Switch (SSS) controller assigns data-type bits when categorizing host accesses as paging files used by memory management, temporary files, File Allocation Table (FAT) and File Descriptor Block (FDB) entries, and user data files, using address ranges and file extensions read from FAT. Paging files and temporary files are never written to flash. Partial-page data is packed and sector mapped by sub-sector mapping tables that are pointed to by a unified mapping table that stores the data-type bits and pointers to data or tables in DRAM. Partial sectors are packed together to reduce DRAM usage and flash wear. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails. | 11-08-2012 |
20130145085 | Virtual Memory Device (VMD) Application/Driver with Dual-Level Interception for Data-Type Splitting, Meta-Page Grouping, and Diversion of Temp Files to Ramdisks for Enhanced Flash Endurance - A Virtual-Memory Device (VMD) driver and application execute on a host to increase endurance of flash memory attached to a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD). Host accesses to flash are intercepted by the VMD driver using upper and lower-level filter drivers and categorized as data types of paging files, temporary files, meta-data, and user data files, using address ranges and file extensions read from meta-data tables. Paging files and temporary files are optionally written to flash. Full-page and partial-page data are grouped into multi-page meta-pages by data type before storage by the SSD. ramdisks and caches for storing each data type in the host DRAM are managed and flushed to the SSD by the VMD driver. Write dates are stored for pages or blocks for management functions. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails. | 06-06-2013 |
20140006688 | Endurance and Retention Flash Controller with Programmable Binary-Levels-Per-Cell Bits Identifying Pages or Blocks as having Triple, Multi, or Single-Level Flash-Memory Cells | 01-02-2014 |
20140281151 | Green NAND Device (GND) Driver with DRAM Data Persistence For Enhanced Flash Endurance and Performance - A Green NAND Device (GND) driver application queries AC line and battery status and then stores an image of processor states and caches and a resume routine to DRAM when power failure occurs. A DRAM image is then stored to flash memory for a persistent mode when battery power is available. The image in DRAM may be a partial image that includes entries, flushed caches, processor contexts, ramdisks, write caches, and a resume context. Endurance of flash memory is increased by a Super Enhanced Endurance Device (SEED) SSD. In a power down mode, the GND driver limits DRAM use and only caches in DRAM data that can be deleted on power down. Host accesses to flash are intercepted by the GND driver and categorized by data type. Paging files and temporary files cached in DRAM are optionally written to flash. | 09-18-2014 |
20140310574 | Green eMMC Device (GeD) Controller with DRAM Data Persistence, Data-Type Splitting, Meta-Page Grouping, and Diversion of Temp Files for Enhanced Flash Endurance - A controller for a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD) increases flash endurance using a DRAM buffer. Host accesses to flash are intercepted by the controller and categorized as data types of paging files, temporary files, meta-data, and user data files, using address ranges and file extensions read from meta-data tables. Paging files and temporary files are optionally written to flash. Full-page and partial-page data are grouped into multi-page meta-pages by data type in the DRAM before storage by lower-level flash devices such as eMMC, UFS, or iSSD. Caches in the DRAM buffer for storing each data type are managed and flushed to the flash devices by the controller. Write dates are stored for pages or blocks for management functions. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails. | 10-16-2014 |