| Patent application number | Description | Published |
|---|
| 20100107717 | METHOD AND DEVICE FOR FABRICATING BONDING WIRES ON THE BASIS OF MICROELECTRONIC MANUFACTURING TECHNIQUES - Bonding wires for sophisticated bonding applications may be efficiently formed on the basis of a corresponding template device that may be formed on the basis of semiconductor material, such as silicon, in combination with associated fabrication techniques, such as lithography and etch techniques. Hence, any appropriate diameter and cross-sectional shape may be obtained with a high degree of accuracy and reliability. | 05-06-2010 |
| 20100136762 | ENHANCING INTEGRITY OF A HIGH-K GATE STACK BY PROTECTING A LINER AT THE GATE BOTTOM DURING GATE HEAD EXPOSURE - Sophisticated gate stacks including a high-k dielectric material and a metal-containing electrode material may be covered by a protection liner, such as a silicon nitride liner, which may be maintained throughout the entire manufacturing sequence at the bottom of the gate stacks. For this purpose, a mask material may be applied prior to removing cap materials and spacer layers that may be used for encapsulating the gate stacks during the selective epitaxial growth of a strain-inducing semiconductor alloy. Consequently, enhanced integrity may be maintained throughout the entire manufacturing sequence, while at the same time one or more lithography processes may be avoided. | 06-03-2010 |
| 20100289083 | MULTI-STEP DEPOSITION OF A SPACER MATERIAL FOR REDUCING VOID FORMATION IN A DIELECTRIC MATERIAL OF A CONTACT LEVEL OF A SEMICONDUCTOR DEVICE - In advanced semiconductor devices, spacer elements may be formed on the basis of a multi-station deposition technique, wherein a certain degree of variability of the various sub-layers of the spacer materials, such as a different thickness, may be applied in order to enhance etch conditions during the subsequent anisotropic etch process. Consequently, spacer elements of improved shape may result in superior deposition conditions when using a stress-inducing dielectric material. Consequently, yield losses due to contact failures in densely packed device areas, such as static RAM areas, may be reduced. | 11-18-2010 |
| 20100330757 | ENHANCED CAP LAYER INTEGRITY IN A HIGH-K METAL GATE STACK BY USING A HARD MASK FOR OFFSET SPACER PATTERNING - When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate height of transistors of different conductivity type when the dielectric cap layers of transistors may have experienced a different process history and may thus require a subsequent adaptation of the final cap layer thickness in one type of the transistors. For this purpose, a hard mask material may be used during a process sequence for forming offset spacer elements in one gate electrode structure while covering another gate electrode structure. | 12-30-2010 |
| 20100330808 | CAP LAYER REMOVAL IN A HIGH-K METAL GATE STACK BY USING AN ETCH PROCESS - In a replacement gate approach, the dielectric cap layers of the gate electrode structures are removed in a separate removal process, such as a plasma assisted etch process, in order to provide superior process conditions during the subsequent planarization of the interlayer dielectric material for exposing the sacrificial gate material. Due to the superior process conditions, the selective removal of the sacrificial gate material may be accomplished with enhanced uniformity, thereby also contributing to superior stability of transistor characteristics. | 12-30-2010 |
| 20110073956 | FORMING SEMICONDUCTOR RESISTORS IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES BY INCREASING ETCH RESISTIVITY OF THE RESISTORS - In a replacement gate approach, the polysilicon material may be efficiently removed during a wet chemical etch process, while the semiconductor material in the resistive structures may be substantially preserved. For this purpose, a species such as xenon may be incorporated into the semiconductor material of the resistive structure, thereby imparting a significantly increased etch resistivity to the semiconductor material. The xenon may be incorporated at any appropriate manufacturing stage. | 03-31-2011 |
| 20110073959 | STRESS ENGINEERING IN A CONTACT LEVEL OF SEMICONDUCTOR DEVICES BY STRESSED CONDUCTIVE LAYERS AND AN ISOLATION SPACER - In sophisticated semiconductor devices, strain-inducing materials having a reduced dielectric strength or having certain conductivity, such as metal nitride and the like, may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors. For this purpose, a strain-inducing material may be efficiently encapsulated on the basis of a dielectric layer stack that may be patterned prior to forming the actual interlayer dielectric material in order to mask sidewall surface areas on the basis of spacer elements. | 03-31-2011 |
| 20110104880 | CORNER ROUNDING IN A REPLACEMENT GATE APPROACH BASED ON A SACRIFICIAL FILL MATERIAL APPLIED PRIOR TO WORK FUNCTION METAL DEPOSITION - In a replacement gate approach, a top area of a gate opening has a superior cross-sectional shape which is accomplished on the basis of a plasma assisted etch process or an ion sputter process. During the process, a sacrificial fill material protects sensitive materials, such as a high-k dielectric material and a corresponding cap material. Consequently, the subsequent deposition of a work function adjusting material layer may not result in a surface topography which may result in a non-reliable filling-in of the electrode metal. In some illustrative embodiments, the sacrificial fill material may also be used as a deposition mask for avoiding the deposition of the work function adjusting metal in certain gate openings in which a different type of work function adjusting species is required. | 05-05-2011 |
| 20110129980 | CAP REMOVAL IN A HIGH-K METAL GATE ELECTRODE STRUCTURE BY USING A SACRIFICIAL FILL MATERIAL - Dielectric cap layers of sophisticated high-k metal gate electrode structures may be efficiently removed on the basis of a sacrificial fill material, thereby reliably preserving integrity of a protective sidewall spacer structure, which in turn may result in superior uniformity of the threshold voltage of the transistors. The sacrificial fill material may be provided in the form of an organic material that may be reduced in thickness on the basis of a wet developing process, thereby enabling a high degree of process controllability. | 06-02-2011 |
