| Patent application number | Description | Published |
|---|
| 20090286375 | METHOD OF FORMING SIDEWALL SPACERS TO REDUCE FORMATION OF RECESSES IN THE SUBSTRATE AND INCREASE DOPANT RETENTION IN A SEMICONDUCTOR DEVICE - A method of forming sidewall spacers for a gate in a semiconductor device includes re-oxidizing/annealing silicon of the substrate and silicon of the gate after formation of the gate. The substrate is re-oxidized by performing an anneal in an inert atmosphere or ambient. The substrate may be re-oxidized/annealing after depositing an oxide layer covering the substrate and gate. Additionally, the substrate may be re-oxidized/annealing after forming the gate without depositing the oxide layer. | 11-19-2009 |
| 20100320509 | Method for forming and integrating metal gate transistors having self-aligned contacts and related structure - According to one exemplary embodiment, a method for forming at least one metal gate transistor with a self-aligned source/drain contact includes forming a metal gate over a substrate. The method further includes forming a source/drain region in the substrate adjacent to the metal gate. The method also includes forming a conformal etch stop layer over the metal gate and the source/drain region. The method further includes forming a source/drain contact over the source/drain region, where the conformal etch stop layer imposes a pre-determined distance between the source/drain contact and the metal gate, thereby causing the source/drain contact to be self-aligned to the metal gate. | 12-23-2010 |
| 20110045648 | METHODS FOR FABRICATING BULK FINFET DEVICES HAVING DEEP TRENCH ISOLATION - Methods are provided for fabricating Bulk FinFET devices having deep trench isolation. One or more deep isolation trenches are formed in a bulk silicon wafer. Mandrel-forming material is deposited overlying the bulk silicon wafer and dielectric pad layer thereon and simultaneously into the trench(es) as filler material. Mandrels are formed, overetching thereof creating a recess at the trench upper end. A conformal sidewall spacer material from which sidewall spacers are fabricated is deposited overlying the mandrels and into the recess forming a spacer overlying the filler material in the trench(es). Mandrels are removed using the spacer as an etch stop. Fin structures are formed from the bulk silicon wafer using the sidewall spacers as an etch mask. The mandrel-forming material is amorphous and/or polycrystalline silicon. | 02-24-2011 |
| 20110068431 | SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING ISOLATION BETWEEN FIN STRUCTURES OF FINFET DEVICES - Semiconductor structures and methods for forming isolation between fin structures formed from a bulk silicon wafer are provided. A bulk silicon wafer is provided having one or more fin structures formed therefrom. Forming of the fin structures defines isolation trenches between the one or more fin structures. Each of the fin structures has vertical sidewalls. An oxide layer is deposited in the isolation trenches and on the vertical sidewalls using HPDCVD in about a 4:1 ratio or greater. The oxide layer is isotropically etched to remove the oxide layer from the vertical sidewalls and a portion of the oxide layer from the bottom of the isolation trenches. A substantially uniformly thick isolating oxide layer is formed on the bottom of the isolation trench to isolate the one or more fin structures and substantially reduce fin height variability. | 03-24-2011 |
| 20110070712 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTIVE RESISTOR STRUCTURE - Methods are provided for fabricating a semiconductor device. A method comprises forming a conductive fin arrangement on a first region of a semiconductor substrate. The method further comprises forming a semiconductive resistor structure on a second region of the semiconductor substrate after forming the conductive fin arrangement, and forming a gate stack foundation structure overlying the conductive fin arrangement after forming the semiconductive resistor structure. The method further comprises removing portions of the gate stack foundation structure overlying the first region of the semiconductor substrate to define a gate structure for the semiconductor device. | 03-24-2011 |
| 20110084336 | SEMICONDUCTOR DEVICE WITH STRESSED FIN SECTIONS, AND RELATED FABRICATION METHODS - A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections. | 04-14-2011 |
| 20110204419 | INTEGRATED CIRCUITS INCLUDING MULTI-GATE TRANSISTORS LOCALLY INTERCONNECTED BY CONTINUOUS FIN STRUCTURE AND METHODS FOR THE FABRICATION THEREOF - Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate and a plurality of locally interconnected multi-gate transistors. The plurality of locally interconnected multi-gate transistors includes a continuous fin structure formed on the substrate and first and second multi-gate transistors formed on the substrate and including first and second fin segments of the continuous fin structure, respectively. The continuous fin structure electrically interconnects the first and second multi-gate transistors. | 08-25-2011 |
| 20110266622 | SEMICONDUCTOR DEVICE WITH STRESSED FIN SECTIONS - A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections. | 11-03-2011 |
