| Patent application number | Description | Published |
|---|
| 20080203571 | BACKSIDE METALLIZATION FOR INTEGRATED CIRCUIT DEVICES - A method of forming backside metallization on a substrate that includes a plurality of integrated circuit die formed on a front side of the substrate is disclosed. The method includes forming an adhesion layer of aluminum or an aluminum alloy on a backside surface of the substrate, forming a barrier metal layer on the adhesion layer and forming a metal layer on the barrier metal layer. An integrated circuit device is also disclosed which includes a substrate having an integrated circuit die formed on a front side of the substrate, an adhesion layer on a backside surface of the substrate, wherein the adhesion layer is aluminum or an aluminum alloy, a barrier metal layer on the adhesion layer and a metal layer on the barrier metal layer. | 08-28-2008 |
| 20090057877 | Semiconductor Device with Gel-Type Thermal Interface Material - Various methods and apparatus for establishing a thermal pathway for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes forming a metal layer on a semiconductor chip and forming a gel-type thermal interface material layer on the metal layer. A solvent and a catalyst material are applied to the metal layer prior to forming the gel-type thermal interface material layer to facilitate bonding between the gel-type thermal interface material layer and the metal layer. | 03-05-2009 |
| 20090140244 | SEMICONDUCTOR DEVICE INCLUDING A DIE REGION DESIGNED FOR ALUMINUM-FREE SOLDER BUMP CONNECTION AND A TEST STRUCTURE DESIGNED FOR ALUMINUM-FREE WIRE BONDING - In sophisticated semiconductor devices including copper-based metallization systems, a substantially aluminum-free bump structure in device regions and a substantially aluminum-free wire bond structure in test regions may be formed on the basis of a manufacturing process resulting in identical final dielectric layer stacks in these device areas. The number of process steps may be reduced by making a decision as to whether a substrate is to become a product substrate or test substrate for estimating the reliability of actual semiconductor devices. For example, nickel contact elements may be formed above copper-based contact areas wherein the nickel may provide a base for wire bonding or forming a bump material thereon. | 06-04-2009 |
| 20090166861 | WIRE BONDING OF ALUMINUM-FREE METALLIZATION LAYERS BY SURFACE CONDITIONING - In sophisticated semiconductor devices including copper-based metallization systems, a substantially aluminum-free bump structure in device regions and a substantially aluminum-free wire bond structure in test regions may be formed on the basis of a manufacturing process resulting in identical final dielectric layer stacks in these device areas. Moreover, reliable wire bond connections may be obtained by providing a protection layer, such as an oxide layer, after exposing the respective contact metal, such as copper, nickel and the like, thereby providing highly uniform process conditions during the subsequent wire bonding process. The number of process steps may be reduced by making a decision as to whether a substrate is to become a product substrate or test substrate for estimating the reliability of actual semiconductor devices. For example, nickel contact elements may be formed above copper-based contact areas wherein the nickel may provide a base for wire bonding or forming a bump material thereon. | 07-02-2009 |
| 20090243105 | WIRE BONDING ON REACTIVE METAL SURFACES OF A METALLIZATION OF A SEMICONDUCTOR DEVICE BY PROVIDING A PROTECTIVE LAYER - In semiconductor devices having a copper-based metallization system, bond pads for wire bonding may be formed directly on copper surfaces, which may be covered by an appropriately designed protection layer to avoid unpredictable copper corrosion during the wire bond process. A thickness of the protection layer may be selected such that bonding through the layer may be accomplished, while also ensuring a desired high degree of integrity of the copper surface. | 10-01-2009 |
| 20100052137 | ENHANCED WIRE BOND STABILITY ON REACTIVE METAL SURFACES OF A SEMICONDUCTOR DEVICE BY ENCAPSULATION OF THE BOND STRUCTURE - The wire bond structure of sophisticated metallization systems, for instance based on copper, may be provided without a terminal aluminum layer and without any passivation layers for exposed copper surfaces by providing a fill material after the wire bonding process in order to encapsulate at least the sensitive metal surfaces and a portion of the bond wire. Hence, significant cost reduction, reduced cycle times and a reduction of the required process steps may be accomplished independently from the wire bond materials used. Thus, integrated circuits requiring a sophisticated metallization system may be connected by wire bonding to the corresponding package or carrier substrate with a required degree of reliability based on a corresponding fill material for encapsulating at least the sensitive metal surfaces. | 03-04-2010 |
| 20100107717 | METHOD AND DEVICE FOR FABRICATING BONDING WIRES ON THE BASIS OF MICROELECTRONIC MANUFACTURING TECHNIQUES - Bonding wires for sophisticated bonding applications may be efficiently formed on the basis of a corresponding template device that may be formed on the basis of semiconductor material, such as silicon, in combination with associated fabrication techniques, such as lithography and etch techniques. Hence, any appropriate diameter and cross-sectional shape may be obtained with a high degree of accuracy and reliability. | 05-06-2010 |
| 20100109158 | SEMICONDUCTOR DEVICE INCLUDING A REDUCED STRESS CONFIGURATION FOR METAL PILLARS - In a metallization system of a sophisticated semiconductor device, metal pillars may be provided so as to exhibit an increased efficiency in distributing any mechanical stress exerted thereon. This may be accomplished by significantly increasing the surface area of the final passivation layer that is in tight mechanical contact with the metal pillar. | 05-06-2010 |
| 20100164098 | SEMICONDUCTOR DEVICE INCLUDING A COST-EFFICIENT CHIP-PACKAGE CONNECTION BASED ON METAL PILLARS - In sophisticated semiconductor devices, a chip-package interconnect structure may be established on the basis of a metal pillar without using a solder bump material in the package. In this case, the complexity of the manufacturing process for forming the wiring system of the package may be significantly reduced, while also providing the possibility of increasing packing density of the pillar structure. | 07-01-2010 |
| 20100207281 | Semiconductor Chip with Reinforcement Layer - Various semiconductor chip reinforcement structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a side and forming a polymer layer on the side. The polymer layer has a central portion and a first frame portion spatially separated from the central portion to define a first channel. | 08-19-2010 |
| 20100301460 | SEMICONDUCTOR DEVICE HAVING A FILLED TRENCH STRUCTURE AND METHODS FOR FABRICATING THE SAME - Methods are provided for packaging a semiconductor die having a first surface. In accordance with an exemplary embodiment, a method comprises the steps of forming a trench in the first surface of the die, electrically and physically coupling the die to a packaging substrate, forming a sealant layer on the first surface of the die, forming an engagement structure within the trench, and infusing underfill between the sealant layer and the engagement structure and the packaging substrate. | 12-02-2010 |
| 20110074031 | BACK SIDE METALLIZATION WITH SUPERIOR ADHESION IN HIGH-PERFORMANCE SEMICONDUCTOR DEVICES - In sophisticated semiconductor devices, the metal-containing layer stack at the back side of the substrate may be provided so as to obtain superior adhesion to the semiconductor material in order to reduce the probability of creating leakage paths in a bump structure upon separating the substrate into individual semiconductor chips. For this purpose, in some illustrative embodiments, an adhesion layer including a metal and at least one non-metal species may be used, such as titanium oxide, in combination with further metal-containing materials, such as titanium, vanadium and gold. | 03-31-2011 |
