| Patent application number | Description | Published |
|---|
| 20090210761 | AC Scan Diagnostic Method and Apparatus Utilizing Functional Architecture Verification Patterns - A method, apparatus and computer program product are provided for implementing AC scan diagnostic of delay and AC scan chain defects in an integrated circuit chip under test using Functional Architecture Verification Patterns (AVPs) for enabling rapidly localizing identified defects to a failing Shift Register Latch (SRL). An Architecture Verification Pattern (AVP) test pattern set is generated using a chip design input and simulation. AVP test vectors are applied for starting chip clocks and initiating testing, such as Logic Built-In-Self-Test (LBIST). | 08-20-2009 |
| 20090210763 | Automated System and Processing for Expedient Diagnosis of Broken Shift Registers Latch Chains Using JTAG - This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product. | 08-20-2009 |
| 20090217112 | AC ABIST Diagnostic Method, Apparatus and Program Product - A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester. | 08-27-2009 |
| 20090307548 | METHOD AND APPARATUS FOR PERFORMING LOGIC BUILT-IN SELF-TESTING OF AN INTEGRATED CIRCUIT - A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly. | 12-10-2009 |
| Patent application number | Description | Published |
|---|
| 20090210761 | AC Scan Diagnostic Method and Apparatus Utilizing Functional Architecture Verification Patterns - A method, apparatus and computer program product are provided for implementing AC scan diagnostic of delay and AC scan chain defects in an integrated circuit chip under test using Functional Architecture Verification Patterns (AVPs) for enabling rapidly localizing identified defects to a failing Shift Register Latch (SRL). An Architecture Verification Pattern (AVP) test pattern set is generated using a chip design input and simulation. AVP test vectors are applied for starting chip clocks and initiating testing, such as Logic Built-In-Self-Test (LBIST). | 08-20-2009 |
| 20090210763 | Automated System and Processing for Expedient Diagnosis of Broken Shift Registers Latch Chains Using JTAG - This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product. | 08-20-2009 |
| 20090217112 | AC ABIST Diagnostic Method, Apparatus and Program Product - A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester. | 08-27-2009 |
| 20090307548 | METHOD AND APPARATUS FOR PERFORMING LOGIC BUILT-IN SELF-TESTING OF AN INTEGRATED CIRCUIT - A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly. | 12-10-2009 |
