Patent application number | Description | Published |
20090186525 | Shell for Circuit Board Connector - The invention relates to a circuit board connector capable of establishing an electrical connection between circuits on a circuit board and a mating electrical connector at a mating side of said circuit board connector. The circuit board connector includes a connector housing accommodating a plurality of terminals for establishing said electrical connection and an electrically conductive shell at least partially enclosing said connector housing. The shell includes a top wall and a rear wall, wherein said rear wall is connected to said top wall and is arranged opposite to said mating side. The shell further has a first and second extension connected to opposite sides of said rear wall and bent with respect to said rear wall to extend towards said mating side. First and second mounting posts are connected, respectively, to said first and second extension and third and fourth mounting posts are connected to said rear wall, wherein said mounting posts are arranged for mounting said shell on said circuit board. | 07-23-2009 |
20110053415 | ELECTRICAL SHIELDING CAGE AND SYSTEM THEREOF - A shielding cage for receiving a plurality of electronic modules includes a bottom cage portion and a plurality of independent upper cage portions each one of which comprising a top wall and two lateral walls adapted to cooperate with the bottom cage portion. Furthermore, each of said upper cage portions defines with the bottom cage portion a respective compartment having an inner cavity for receiving an electronic module, and a subdivision of said bottom cage portion provides for a bottom wall of said compartment. | 03-03-2011 |
20110151700 | Card Connector - The connector of the present invention includes a base having a plurality of terminals for contacting the card and a cover for holding the card. In an embodiment, the base has two resilient plates extending from the base, each of the plates has a distal end at which an inner hinging portion is formed. The cover has an outer hinging portion engaged with the inner hinging portions to form a hinge such that the cover is pivotally mounted on the base and movable in relation to the base. Each of the resilient plates is L-shaped such that the hinge is deflectable from the base. | 06-23-2011 |
20110250790 | SHIELDED CONNECTOR - The present invention provides a shielding assembly for a connector assembly including a connector and a counterpart connector. The shielding assembly includes a shield member having a shield wall and at least one spring element for making electrical contact between the shield wall and the counterpart connector along a first electrical conduction path in the mated situation of the connector and the counterpart connector. The spring element includes a first portion being configured for making electrical contact with the counterpart connector and a second portion for providing a spring force to the first portion. The spring element is configured for having at least a first position in the unmated situation of the connector and the counterpart connector and a second position in the mated situation of the connector and the counterpart connector, such that in the first position the second portion is arranged at a first separation from the shield wall and in the second position the second portion is arranged at a second separation from the shield wall, wherein the second separation is larger than the first separation. | 10-13-2011 |
Patent application number | Description | Published |
20130328150 | ADJUSTABLE AVALANCHE DIODE IN AN INTEGRATED CIRCUIT - An avalance diode including, between two heavily-doped regions of opposite conductivity types arranged at the surface of a semiconductor region, a lightly-doped region, with length L of the lightly-doped region between the heavily-doped regions approximately ranging between 50 and 200 nm. | 12-12-2013 |
20140015002 | MOS TRANSISTOR ON SOI PROTECTED AGAINST OVERVOLTAGES - A MOS transistor protected against overvoltages formed in an SOI-type semiconductor layer arranged on an insulating layer itself arranged on a semiconductor substrate including a lateral field-effect control thyristor formed in the substrate at least partly under the MOS transistor, a field-effect turn-on region of the thyristor extending under at least a portion of a main electrode of the MOS transistor and being separated there-from by said insulating layer, the anode and the cathode of the thyristor being respectively connected to the drain and to the source of the MOS transistor, whereby the thyristor turns on in case of a positive overvoltage between the drain and the source of the MOS transistor. | 01-16-2014 |
20140015052 | ON-SOI integrated circuit comprising a thyristor (SCR) for protection against electrostatic discharges - An integrated circuit includes an UTBOX insulating layer under and plumb with first and second electronic components, and corresponding ground planes and oppositely-doped wells made plumb with them. The wells contact with corresponding ground planes. A pair of oppositely doped bias electrodes, suitable for connecting corresponding bias voltages, contacts respective wells and ground planes. A third electrode contacts the first well. A first trench isolates one bias electrode from the third electrode and extends through the layer and into the first well. A second trench isolates the first bias electrode from one component. This trench has an extent that falls short of reaching an interface between the first ground plane and the first well. | 01-16-2014 |
20140017821 | On-SOI integrated circuit comprising a triac for protection against electrostatic discharges - An integrated circuit includes four electronic components, a buried UTBOX layer under and plumb with the electronic components, and two pairs of oppositely doped ground planes plumb with corresponding components under the layer. A first isolation trench mutually isolates the ground planes from corresponding wells made plumb and in contact with the ground planes and exhibiting the first doping type. Bias electrodes contact respective wells and ground planes. One pair of electrodes is for connecting to a first bias voltage and the other pair is for connecting to a second bias voltage. Also included are a semiconductor substrate exhibiting the first type of doping and a deeply buried well exhibiting the second type of doping. The deeply buried well contacts the other wells and separates them from the substrate. Finally, a control electrode couples to the deeply buried well. | 01-16-2014 |
20140017856 | On-SOI integrated circuit comprising a subjacent protection transistor - An integrated circuit features a FET, an UTBOX layer plumb with the FET, an underlayer ground plane with first doping plumb with the FET's gate and channel, first and second underlayer semiconducting elements, both plumb with the drain or source, electrodes in contact respectively with the ground plane and with the first element, one having first doping and being connected to a first voltage, the other having the first doping and connected to a second bias voltage different from the first, a semiconducting well having the second doping and plumb with the first ground plane and both elements, a first trench isolating the first FET from other components of the integrated circuit and extending through the layer into the well, and second and third trenches isolating the FET from the electrodes, and extending to a depth less than a plane/well interface. | 01-16-2014 |
20140017858 | On-SOI integrated circuit comprising a lateral diode for protection against electrostatic discharges - An integrated circuit includes a transistor, an UTBOX buried insulating layer disposed under it, a ground plane disposed under the layer, a well disposed under the plane, a first trench made at a periphery of the transistor and extending through the layer and into the well, a substrate situated under the well, a p-n diode made on a side of the transistor and comprising first and second zones of opposite doping, the first zone being configured for electrical connection to a first electrode of the transistor, wherein first and second zones are coplanar with the plane, a second trench for separating the first and second zones, the second trench extending through the layer into the plane and until a depth less than an interface between the plane and the well, and a third zone under the second trench forming a junction between the zones. | 01-16-2014 |
20140017871 | Integrated circuit on SOI comprising a bipolar transistor with isolating trenches of distinct depths - An integrated circuit includes a semiconductor substrate, a silicon layer, a buried isolating layer arranged between the substrate and the layer, a bipolar transistor comprising a collector and emitter having a first doping, and a base and a base contact having a second doping, the base forming a junction with the collector and emitter, the collector, emitter, base contact, and the base being coplanar, a well having the second doping and plumb with the collector, emitter, base contact and base, the well separating the collector, emitter and base contact from the substrate, having the second doping and extending between the base contact and base, a isolating trench plumb with the base and extending beyond the layer but without reaching a bottom of the emitter and collector, and another isolating trench arranged between the base contact, collector, and emitter, the trench extending beyond the buried layer into the well. | 01-16-2014 |
20140319648 | INTEGRATED CIRCUIT ON SOI COMPRISING A TRANSISTOR PROTECTING FROM ELECTROSTATIC DISCHARGES - An integrated circuit includes first and second electronic components, a buried UTBOX insulating layer, first and second ground planes plumb with the first and second electronic components, first and second wells, first and second biasing electrodes making contact with the first and second wells and with the first and second ground planes, a third electrode making contact with the first well, a first trench isolation separating the first and third electrodes and extending through the buried insulating layer as far as into the first well, and a second trench isolation that isolates the first electrode from the first component, and that does not extend as far as the interface between the first ground plane and the first well. | 10-30-2014 |
20150061023 | On-SOI integrated circuit equipped with a device for protecting against electrostatic discharges - The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater. | 03-05-2015 |
20150084092 | OVERVOLTAGE PROTECTION COMPONENTS IN AN OPTOELECTRONIC CIRCUIT ON SOI - An overvoltage protection component may be in a SOI layer, a portion of the SOI layer forming the core of an optical waveguide. This component may be made of semiconductor regions of different doping types and/or levels, at least one of these regions corresponding to at least a portion of the waveguide core. | 03-26-2015 |
20150086154 | OVERVOLTAGE PROTECTION COMPONENT AND AN ASSEMBLY OF INTEGRATED CIRCUIT CHIPS HAVING SAID OVERVOLTAGE PROTECTION COMPONENT - A device includes integrated circuit chips mounted on one another. At least one component for protecting elements of a second chip is formed in a first chip. The chips may be of the SOI type, with the first chip including a first SOI layer having a first thickness and the second chip including a second SOI layer having a second thickness smaller than the first thickness. The first chip including the component for protecting may include an optical waveguide with the component for protecting formed adjacent the optical waveguide. | 03-26-2015 |
20150279883 | VERTICAL GATE TRANSISTOR AND PIXEL STRUCTURE COMPRISING SUCH A TRANSISTOR - The present disclosure relates to a photodiode comprising: a P-conductivity type substrate region, an electric charge collecting region for collecting electric charges appearing when a rear face of the substrate region receives light, the collecting region comprising an N-conductivity type region formed deep in the substrate region, an N-conductivity type read region formed in the substrate region, and an isolated transfer gate, formed in the substrate region in a deep isolating trench extending opposite a lateral face of the N-conductivity type region, next to the read region, and arranged for receiving a gate voltage to transfer electric charges stored in the collecting region toward the read region. | 10-01-2015 |