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Fong-Yuan
Fong-Yuan Chang, Chu-Dong Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20110107278 | Method for Improving Yield Rate Using Redundant Wire Insertion - A method and apparatus for manufacturing an integrated circuit (IC), the method including, generating, by a graphical construction unit, a first graph corresponding to a first net of the IC, the first graph representing a pin of the first net as a vertex, and a connection between two pins of the first net as an edge, the first graph further corresponding to a first IC layout; identifying a first and a second pair of unconnected vertices in the first graph for inserting a first and a second redundant edge, respectively, the first redundant edge and the second redundant edge forming a first connected loop and a second connected loop, respectively, each loop further including at least two edges of the first graph; calculating a tolerance ratio for the first redundant edge and the second redundant edge; sorting the first and second redundant edge based on their tolerance ratio; calculating a yield rate change of the first IC layout associated with inserting one of the first or second redundant edge with a highest tolerance ratio, and updating the first IC layout to include the redundant edge with the highest tolerance ratio if the yield rate change is greater than zero; and calculating the yield rate change of the first IC layout associated with inserting the first or second redundant edge having a second highest tolerance ratio, and updating the first IC layout to include the redundant edge with the second highest tolerance ratio if the yield rate change is greater than zero. | 05-05-2011 |
| 20110154282 | SYSTEMS AND METHODS FOR DESIGNING AND MAKING INTEGRATED CIRCUITS WITH CONSIDERATION OF WIRING DEMAND RATIO - A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described. | 06-23-2011 |
Fong-Yuan Chang, Taichang TW
| Patent application number | Description | Published |
|---|---|---|
| 20090178013 | SYSTEM FOR IMPLEMENTING POST-SILICON IC DESIGN CHANGES - An engineering change order (ECO) modifying an IC having spare cell instances is implemented by converting active cell instances implementing portions of the IC to be deleted into additional spare cell instances, by creating a technology independent behavioral model of portions of the IC to be added, by selecting spare cell instances to implement the behavior model, and by routing nets to the selected spare cell instances in a way that minimizes a number of metal layers of the IC that are modified. | 07-09-2009 |
Fong-Yuan Wen, Taoyuan City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090189179 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE PACKAGE - A method for manufacturing flip-chip light emitting diode (LED) package. A recess array is formed at the top surface of a silicon wafer. Two through-wafer via holes are formed in the recess. A plurality of LED chips are flip-chip mounted in each of the recesses, respectively. Two electrodes of each LED chip are respectively covered the two via holes. An encapsulator for encapsulating each LED chip is arranged in the recess to provide a flat top surface. A metal layer is deposited on the bottom surface of the silicon wafer to electrically connecting with the electrodes through the two via holes. Metal lines which electrically connecting the electrodes are formed by patterning the metal layer. A plurality of silicon submounts, each including at least one recess, are cut off from the silicon wafer. A fluorescent layer is arranged on the top surface of the encapsulator. | 07-30-2009 |
| 20100254140 | LAMP HOLDER OF LED STREETLAMP WITH HEAT-CONDUCTING AND HEAT-DISSIPATING CAPABILITY - A lamp holder of a LED streetlamp includes a lamp cover, a LED unit and a plurality of heat-conducting posts. The LED unit is provided below the lamp cover. A transparent lamp cover covers outside the LED unit. Further, the heat-conducting posts are arranged upright in the lamp cover and separated from each other by a distance. Each of the heat-conducting posts is connected to the inner edge surface of the lamp cover opposite to the LED unit and extends toward the top edge of the lamp cover to be located between the top and bottom of the lamp cover. On both sides of the lamp cover laterally facing the heat-conducting posts, venting holes are provided to form an open structure, thereby allowing outside air to enter the lamp cover and flow among the heat-conducting posts. | 10-07-2010 |
| 20100277926 | LIGHT GUIDING DIFFUSER - A light guiding diffuser used for assembling with a light emitting diode module to form an illuminating light source. The light guiding diffuser includes an elliptical ring-shaped base portion and a convex portion extended from a surface of the base portion and formed a space with the base portion for accommodating the light emitting diode module. The convex portion has a cross section which has a minimum thickness in a center thereof and the thickness of the cross section continuous increases from the center toward the base portion. | 11-04-2010 |