Patent application number | Description | Published |
20090077344 | Method for bus testing and addressing in mass memory components - A method and apparatus for addressing a plurality of mass memory components coupled to a host device. The memory components can be arranged in a chain or in a ring configuration. In a ring, each memory component receives a bit pattern from the preceding stage and sends a bit pattern to the next stage in consecutive clock periods. Based on the received bit pattern, a recipient component knows the bus width between itself and the sending component. In a chain, each memory component also sends the received bit pattern back to the preceding stage. The memory component can generate its own address by counting clock periods. Alternatively, a recipient component changes its received bit pattern before sending the bit pattern to the next stage. As such, the recipient component knows its address based on the received bit pattern. | 03-19-2009 |
20090094678 | Mulimode device - A mode indexing table is used for listing the available modes in a multimode device. From information in the mode indexing table, a host recognizes the modes as listed in the table. The host has a mandatory initialization mode using a known technique, such that the device can enter into an initialization mode directly or via a boot function. During initialization, the host receives the remaining part of the table from the multi-mode device and recognizes the functionality of each of the listed modes in the table. Among the available modes, some modes are allowed to access data of other modes according to the level of access. The multimode device has some commands that can be used for direct mode switching. | 04-09-2009 |
20130019065 | Mobile Memory Cache Read OptimizationAANM Floman; MattiAACI KangasalaAACO FIAAGP Floman; Matti Kangasala FIAANM Mylly; KimmoAACI YlojarviAACO FIAAGP Mylly; Kimmo Ylojarvi FI - A method for enabling cache read optimization for mobile memory devices is described. The method includes receiving one or more access commands, at a memory device from a host, the one or more access commands instructing the memory device to access at least two data blocks. The at least two data blocks are accessed. The method includes generating, by the memory device, pre-fetch information for the at least two data blocks based at least in part on an order of accessing the at least two data blocks. Apparatus and computer readable media are also described. | 01-17-2013 |
20130024601 | User Selectable Balance Between Density and Reliability - A method for enabling users to select a configuration balance for a memory device is described. The method includes receiving an indication of a memory configuration for a mass memory including two or more of memory cells. One or more memory cells of the mass memory are selected based at least in part on 1) the indication, 2) a current configuration for each of the one or more memory cells and 3) a program-erase count for each of the one or more memory cells. The method also includes determining a new configuration for each of the selected one or more memory cells. For each of the selected one or more memory cells, the configuration of the memory cell is changed from the current configuration to the determined new configuration. Apparatus and computer readable media are also disclosed. | 01-24-2013 |
20130346668 | Virtual Memory Module - A memory controller of a mass memory device determining that a memory operation has been initiated which involves the mass memory device, and in response dynamically checks for available processing resources of a host device that is operatively coupled to the mass memory device and thereafter puts at least one of the available processing resources into use for performing the memory operation. In various non-limiting examples: the available processing resources may be a core engine of a multi-core CPU, a DPS or a graphics processor; central processing unit; a digital signal processor; and a graphics processor; and it may also be dynamically checked whether memory resources of the host are available and those can be similarly put into use (e.g., write data to a DRAM of the host, process data in the DRAM with the host DSP, then write the processed data to the mass memory device). | 12-26-2013 |
20140006719 | MOBILE MEMORY CACHE READ OPTIMIZATION | 01-02-2014 |
20140181382 | User Selectable Balance Between Density and Reliability - A method for enabling users to select a configuration balance for a memory device is described. The method includes receiving an indication of a memory configuration for a mass memory including two or more of memory cells. One or more memory cells of the mass memory are selected based at least in part on 1) the indication, 2) a current configuration for each of the one or more memory cells and 3) a program-erase count for each of the one or more memory cells. The method also includes determining a new configuration for each of the selected one or more memory cells. For each of the selected one or more memory cells, the configuration of the memory cell is changed from the current configuration to the determined new configuration. Apparatus and computer readable media are also disclosed. | 06-26-2014 |