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Flaker, US
Anne Flaker, Essex Junction, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20090273988 | CIRCUIT AND METHODS TO IMPROVE THE OPERATION OF SOI DEVICES - According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground. This would enable the circuit to retain most of the speed advantages associated with SOI devices while overcoming the loading problem described above. With this preferred embodiment of the present invention, the major delay caused by the bipolar loading effect is minimized while the speed advantage due to providing a lower, variable V | 11-05-2009 |
Bruce Flaker, Essex Junction, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20090273988 | CIRCUIT AND METHODS TO IMPROVE THE OPERATION OF SOI DEVICES - According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground. This would enable the circuit to retain most of the speed advantages associated with SOI devices while overcoming the loading problem described above. With this preferred embodiment of the present invention, the major delay caused by the bipolar loading effect is minimized while the speed advantage due to providing a lower, variable V | 11-05-2009 |
Christopher S. Flaker, Springville, UT US
| Patent application number | Description | Published |
|---|---|---|
| 20110056233 | Recreational Cooler - A recreational cooler with a hollow accessory shaft is disclosed. The hollow shaft extends completely through the cooler from top to bottom. The hollowed area of the shaft is completely independent from the product receiving area of the cooler allowing for insertion of recreational cooler accessories. Recreational cooler accessories may include: umbrellas, fishing poles, radios, tables, cooking stands, seats, chairs, beverage bottles, cans, cups, basketball standards, and/or racks for drying beach towels. Two coolers may also be used to support each side of a volleyball net, badminton net, or tennis net. | 03-10-2011 |
Heather Flaker, Essex Junction, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20090273988 | CIRCUIT AND METHODS TO IMPROVE THE OPERATION OF SOI DEVICES - According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground. This would enable the circuit to retain most of the speed advantages associated with SOI devices while overcoming the loading problem described above. With this preferred embodiment of the present invention, the major delay caused by the bipolar loading effect is minimized while the speed advantage due to providing a lower, variable V | 11-05-2009 |
Richard W. Flaker, Fairfield, OH US
| Patent application number | Description | Published |
|---|---|---|
| 20080295849 | ENDOSCOPIC BITE BLOCK FOR USE WITH CANNULA - A bite block that is inserted into a patient's mouth during an endoscopic diagnostic or surgical procedure that has a channel for receiving an endoscope or other surgical instrument through the patient's mouth and additional channels transmitting a gas to the patient and transmitting expired gas from the patient. | 12-04-2008 |
| 20090133699 | ORAL NASAL CANNULA - Disclosed is a respiratory cannula assembly to deliver and receive gases from a patient. The cannula assembly contains two oral prongs for delivering and receiving gases from the patient as well as at least one gas delivery nasal prong and at least one gas receiving nasal prong. The gas receiving nasal prong extends further into the patients nostril than the gas delivery nasal prong. The cannula assembly further contains a connector that aids in coupling to a medical device, the connector including independent oral and nasal moisture traps that remove moisture from exhaled patient gases. | 05-28-2009 |
Scott Flaker, Essex Junction, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20090273988 | CIRCUIT AND METHODS TO IMPROVE THE OPERATION OF SOI DEVICES - According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground. This would enable the circuit to retain most of the speed advantages associated with SOI devices while overcoming the loading problem described above. With this preferred embodiment of the present invention, the major delay caused by the bipolar loading effect is minimized while the speed advantage due to providing a lower, variable V | 11-05-2009 |
Shirley A. Flaker, Essex Junction, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20090273988 | CIRCUIT AND METHODS TO IMPROVE THE OPERATION OF SOI DEVICES - According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground. This would enable the circuit to retain most of the speed advantages associated with SOI devices while overcoming the loading problem described above. With this preferred embodiment of the present invention, the major delay caused by the bipolar loading effect is minimized while the speed advantage due to providing a lower, variable V | 11-05-2009 |