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Flaitz
Philip Flaitz, Newburgh, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100084624 | Dielectric mesh isolated phase change structure for phase change memory - A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure. | 04-08-2010 |
Philip L. Flaitz, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100311236 | COPPER INTERCONNECT STRUCTURE WITH AMORPHOUS TANTALUM IRIDIUM DIFFUSION BARRIER - A method of forming a diffusion barrier for use in semiconductor device manufacturing includes depositing, by a physical vapor deposition (PVD) process, an iridium doped, tantalum based barrier layer over a patterned interlevel dielectric (ILD) layer, wherein the barrier layer is deposited with an iridium concentration of at least 60% by atomic weight such that the barrier layer has a resulting amorphous structure. | 12-09-2010 |
Philip L. Flaitz, Newburgh, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080254643 | STRUCTURE TO IMPROVE ADHESION BETWEEN TOP CVD LOW-K DIELECTRIC AND DIELECTRIC CAPPING LAYER - An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiO | 10-16-2008 |