| Patent application number | Description | Published |
|---|
| 20090200654 | Method of electrically connecting a microelectronic component - A microelectronic assembly is provided which can include an element including a first dielectric layer and a second dielectric layer overlying the first dielectric layer, the second dielectric layer having an exposed surface defining an exposed major surface of the element. A plurality of substantially rigid metal posts can project beyond the exposed surface, the metal posts having ends remote from the exposed surface. The microelectronic assembly can include a microelectronic device which has bond pads and overlies the element. The microelectronic device can have a major surface which confronts the posts. Connections electrically connect the ends of the metal posts with the bond pads of the microelectronic device. | 08-13-2009 |
| 20090200655 | Method of electrically connecting a microelectronic component - A microelectronic unit can include a support structure including a dielectric having oppositely-directed first and second surfaces. A plurality of substantially rigid posts can protrude parallel to one another in a direction beyond the first surface of the support structure. Each post may have a top surface remote from the support structure, and the top surfaces can be substantially coplanar with one another. A microelectronic device having a surface with bond pads can overlie the second surface of the support structure with the bond pad-bearing surface of the microelectronic device facing toward the support structure. Connections can electrically connect the posts with the bond pads. | 08-13-2009 |
| 20090236406 | Method of electrically connecting a microelectronic component - A method of treating a component can include providing a component including a plurality of metallic posts extending generally parallel to one another. The providing step can be performed so that the posts have solder on the tips of the posts but not covering other portions of the posts. The method can include reflowing the solder provided on the posts so that the solder coats the posts. The providing step may be performed so that, prior to the reflowing step, the solder covers only the tips of the posts. The providing step can include depositing portions of the solder on a surface of a metallic sheet and etching the sheet from the surface. The plurality of posts may comprise elongated posts. | 09-24-2009 |
| 20100035382 | Methods of making compliant semiconductor chip packages - A method of making a semiconductor chip package is provided in which a compliant layer is provided over a contact bearing face of a semiconductor chip. The compliant layer can have a bottom surface adjacent to the chip face, a top surface facing away from the bottom surface, and at least one sloping surface between the top and bottom surfaces. The compliant layer can be disposed remote in a lateral direction along the contact bearing face from at least one contact adjacent to the sloping surface. Bond ribbons can be formed atop the compliant layer, wherein each bond ribbon electrically connects one of the contacts to an associated conductive terminal at the top surface of the compliant layer. The compliant layer can provide stress relief to the bond ribbons, such as during handling and affixing the assembly to an external substrate. A bond ribbon can include a strip extending along the sloping surface of the compliant layer, the strip having a substantially constant thickness in a direction extending away from the sloping surface. | 02-11-2010 |
| 20110095441 | MICROELECTRONIC ASSEMBLIES HAVING COMPLIANT LAYERS - A compliant semiconductor chip package assembly includes a semiconductor chip having a plurality of chip contacts, and a compliant layer having a top surface, a bottom surface and sloping peripheral edges, whereby the bottom surface of the compliant layer overlies a surface of the semiconductor chip. The assembly also includes a plurality of electrically conductive traces connected to the chip contacts of the semiconductor chip, the traces extending along the sloping edges to the top surface of the compliant layer. The assembly may include conductive terminals overlying the semiconductor chip, with the compliant layer supporting the conductive terminals over the semiconductor chip. The conductive traces have first ends electrically connected with the contacts of the semiconductor chip and second ends electrically connected with the conductive terminals. The conductive terminals are movable relative to the semiconductor chip. | 04-28-2011 |
