Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Fishburn
Bradley R. Fishburn, Nappanee, IN US
| Patent application number | Description | Published |
|---|---|---|
| 20090031939 | Pontoon boat having improved buoyancy - A pontoon boat is shown which includes a frame, and a plurality of pontoons attached to the frame. The plurality of pontoons comprises two outer pontoons of substantially cylindrical configuration and a center pontoon comprising a substantially curvilinear configuration, wherein a height of the center pontoon is substantially equal to the diameter of the outer pontoons. One embodiment of the pontoon is elliptical in cross section. | 02-05-2009 |
C. Simone Fishburn, Redwood City, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100210676 | Chemically Modified Small Molecules - Methods of modifying the rate of systemic absorption of a drug administered to a subject by a pulmonary route, the method comprising covalently conjugating a hydrophilic polymer to a drug, wherein the drug has a half-life of elimination from the lung of less than about 180 minutes, to form a drug-polymer conjugate, wherein the drug-polymer conjugate has a net hydrophilic character and a weight average molecular weight of from about 50 to about 20,000 Daltons, and wherein the half-life of elimination from the lung of the drug-polymer conjugate is at least about 1.5-fold greater than the half-life of elimination from the lung of the drug, wherein the half-life of elimination from the lung is measured by bronchoalveolar lavage followed by assaying residual lung material. | 08-19-2010 |
Douglas C. Fishburn, Hornby CA
| Patent application number | Description | Published |
|---|---|---|
| 20100058657 | GREEN ROOF EDGING AND RESTRAINT SYSTEM - An edging system for green roofing applications defines the margin between grow medium zones and vegetative free zones. An edge and restraint system comprises a edging structure having a substantially upright section having a height and a base section extending laterally from a the middle or lower end of the upright section on at least one lateral side thereof. The base section extends substantially perpendicularly from the upright section. The upright section and base sections may or may not include openings therethrough to allow drainage of water and the like. The upper end of the upright section is adapted to allow a restrainer piece to be releasably secured thereto in snap fit engagement. An edge of a water permeable fabric, which extends between a grow medium and drainage board upon which the grow medium is contained, is essentially secured in place at one end thereof by positioning an end portion thereof which extends from under the grow medium under the restrainer piece as it is snapped in place upon the upright section. | 03-11-2010 |
Fred Fishburn, Woodbridge, VA US
| Patent application number | Description | Published |
|---|---|---|
| 20110280077 | MULTI-SEMICONDUCTOR MATERIAL VERTICAL MEMORY STRINGS, STRINGS OF MEMORY CELLS HAVING INDIVIDUALLY BIASABLE CHANNEL REGIONS, MEMORY ARRAYS INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSING AND FORMING THE SAME - Multi-semiconductor vertical memory strings, strings of memory cells having individually biasable channel regions, arrays incorporating such strings and methods for forming and accessing such strings are provided. For example non-volatile memory devices are disclosed that utilize NAND strings of serially-connected non-volatile memory cells. One such string can include two or more serially connected non-volatile memory cells each having a channel region. Each memory cell of the two or more serially connected non-volatile memory cells shares a common control gate and each memory cell of the two or more serially connected non-volatile memory cells is configured to receive an individual bias to its channel region. | 11-17-2011 |
Fred Fishburn, Manassas, VA US
| Patent application number | Description | Published |
|---|---|---|
| 20100009512 | METHODS OF FORMING A PLURALITY OF CAPACITORS - A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two masking steps is used to form an array of first openings over a plurality of storage node contacts. A later of the two masking steps is used to form an array of second openings received partially over and partially offset from the array of first openings. Overlapping portions of the first and second openings are received over the storage node contacts. After both of the two masking steps, conductive material of the individual capacitor electrodes is deposited into the overlapping portions of each of the first and second openings. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated. | 01-14-2010 |
| 20100266962 | Methods Of Forming A Plurality Of Capacitors - A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two masking steps is used to form an array of first openings over a plurality of storage node contacts. A later of the two masking steps is used to form an array of second openings received partially over and partially offset from the array of first openings. Overlapping portions of the first and second openings are received over the storage node contacts. After both of the two masking steps, conductive material of the individual capacitor electrodes is deposited into the overlapping portions of each of the first and second openings. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated. | 10-21-2010 |
Fred Fishburn, Boise, ID US
| Patent application number | Description | Published |
|---|---|---|
| 20120025385 | Low Resistance Peripheral Local Interconnect Contacts with Selective Wet Strip of Titanium - Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided. | 02-02-2012 |
Fred D. Fishburn, Boise, ID US
| Patent application number | Description | Published |
|---|---|---|
| 20100190314 | Methods Of Forming Semiconductor Structures - Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode. | 07-29-2010 |
| 20100297822 | Methods of forming capacitor structures, methods of forming threshold voltage implant regions, and methods of implanting dopant into channel regions - The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location. | 11-25-2010 |
Fredrick David Fishburn, Woodbridge, VA US
| Patent application number | Description | Published |
|---|---|---|
| 20110318903 | MANUFACTURING METHOD FOR FIN-FET HAVING FLOATING BODY - A manufacturing method for a FIN-FET having a floating body is disclosed. The manufacturing method of this invention includes forming openings in a poly crystalline layer; extending the openings downward; forming spacers on sidewalls of the openings; performing an isotropic silicon etching process on bottoms of the openings; performing deposition by using TEOS to form gate oxide. | 12-29-2011 |
Richard C. Fishburn, Grafton, OH US
| Patent application number | Description | Published |
|---|---|---|
| 20080241478 | Decorative Products Created by Lazing Graphics and Patterns Directly on Substrates with Painted Surfaces - A painted surface is processed by a laser beam to remove at least one layer of paint. The surface that is exposed may be the raw substrate material, e.g., wood or wood laminate, or may be another painted surface. The laser may engrave a pattern, e.g. a wood grain pattern. | 10-02-2008 |
Stephen Fishburn, Maple Valley, WA US
| Patent application number | Description | Published |
|---|---|---|
| 20110289186 | SYSTEMS, METHODS AND ARTICLES FOR PROVIDING COMMUNICATIONS AND SERVICES VIA A PEER-TO-PEER NETWORK OVER A DATA TRANSPORT LINK - Network communications, Web-based services and customized services using the Web-based services may be provided over a peer-to-peer network from a first peer to a second peer (e.g., automobile head unit) wherein the first peer has a separate connection to a more general server-based network such as the Internet. A communications device application based on a peer communications framework component in communication with a peer network stack on the communications device may work as middleware, with a connection to both a more general server-based network such as the Internet and to an external device, such as a head unit of an automobile. Although the communications device has a separate connection out to the Internet via a general network stack co-existing on the same communications device, the peer network stack and the general network stack are not directly connected. | 11-24-2011 |