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Finkler, US
Ofer Finkler, Atlanta, GA US
| Patent application number | Description | Published |
|---|---|---|
| 20110055986 | Athermal Atomic Force Microscope Probes - An atomic force microscopy system includes an imaging probe having a first thermal displacement constant and a sample placement surface. At least a portion of the sample placement surface has a second thermal displacement constant. The sample placement surface is spaced apart from the imaging probe at a predetermined displacement. The sample placement surface is configured so that the second thermal displacement constant matches the first thermal displacement constant so that when the imaging probe and the sample placement surface are subject to a predetermined temperature, both the portion of the sample placement surface and the imaging prove are displaced by a same distance. | 03-03-2011 |
Ulrich Finkler, Mahopac, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090231343 | Exact Geometry Operations on Shapes Using Fixed-Size Integer Coordinates - Techniques for improving efficiency and accuracy of computer-aided design are provided. In one aspect, a method for generating a computer-based representation of a design having one or more shapes is provided comprising the following steps. Each of the shapes in the design is represented with one or more trapezoids, wherein a fixed number of non-vertical lines are used to define an x-coordinate of a left and right base and sides of each trapezoid with intersection points being formed between the non-vertical lines that define the sides. The x-coordinates and intersection points are used to divide the trapezoids into disjoint trapezoids, wherein each disjoint trapezoid is defined by a combination of the same non-vertical lines that are used to define one or more of the trapezoids. An order is assigned to the x-coordinates and intersection points, wherein the x-coordinates and intersection points in the assigned order are representative of the design. | 09-17-2009 |
Ulrich A. Finkler, Yorktown Heights, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110077916 | Method of Distributing a Random Variable Using Statistically Correct Spatial Interpolation Continuously With Spatially Inhomogeneous Statistical Correlation Versus Distance, Standard Deviation, and Mean - Methods for modeling a random variable with spatially inhomogenous statistical correlation versus distance, standard deviation, and mean by spatial interpolation with statistical corrections. The method includes assigning statistically independent random variable to a set of seed points in a coordinate frame and defining a plurality of test points at respective spatial locations in the coordinate frame. A equation for a random variable is determined for each of the test points by spatial interpolation from one or more of the random variable assigned to the seed points. The method further includes adjusting the equation of the random variable at each of the test point with respective correction factor equations. | 03-31-2011 |
Ulrich A. Finkler, Mahopac, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080244493 | PATTERN BASED ELABORATION OF HIERARCHICAL L3GO DESIGNS - A system, method and program product that utilizes flat pattern based L3GO elaboration in a hierarchical environment to create a nested conventional layout. A system is provide for processing a glyph layout to generate shapes for use in a VLSI (very large scale integrated circuit) design process, including: a hierarchical pattern search system that matches patterns from a pattern library to a set of glyph data, wherein the patterns have dependencies that cross hierarchical design boundaries; and a target shape generation system that selects patterns from a set of matching patterns and generates associated shapes. | 10-02-2008 |
| 20090204930 | IPHYSICAL DESIGN SYSTEM AND METHOD - A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency. | 08-13-2009 |
| 20100058265 | Parallel Intrusion Search in Hierarchical VLSI Designs with Substituting Scan Line - Mechanisms are provided for performing intrusion searching of a hierarchical integrated circuit design. These mechanisms may receive the hierarchical integrated circuit design and perform a parallel intrusion search operation, that utilizes a substituting scan line, on the hierarchical integrated circuit design to identify intrusions of geometric objects in the hierarchical integrated circuit design. The mechanisms may further record intrusions of geometric objects in the hierarchical integrated circuit design identified by the parallel intrusion search operation. The parallel intrusion search operation may utilize a plurality of separate intrusion searches executed by the data processing system in parallel on the hierarchical integrated circuit design. | 03-04-2010 |
Ulrich Alfons Finkler, Mahopac, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100017791 | PROBABILISTIC FRAMEWORK FOR THE HIGHLY EFFICIENT CORRELATION OF CALL CHAINS WITH HARDWARE EVENTS - A system and method for correlation of resources with hardware events includes event driven sampling a call chain of functions at to determine when functions of the call chain are active. The call chain is mapped to execution times based upon a probabilistic integration of the functions such that when portions of the call chain are active, resources associated with call chain activity are correlated with hardware events. | 01-21-2010 |
| 20110022815 | STORAGE ALLOCATION - Techniques for storage allocation of a data record are provided. The techniques include attempting to identify a first location for storing a data record, wherein the data record comprises one or more data record attributes, if the first location is identified, selecting the first location for storing the data record, and if the first location is not identified, identifying a second location for storing the data record using a cost penalty function and selecting the second location for storing the data record based on the cost penalty function. | 01-27-2011 |