Fernsler, US
Kimberly Fernsler, Round Rock, TX US
Patent application number | Description | Published |
---|---|---|
20100146214 | METHOD AND SYSTEM FOR EFFICIENT CACHE LOCKING MECHANISM - Systems and methods for the implementation of more efficient cache locking mechanisms are disclosed. These systems and methods may alleviate the need to present both a virtual address (VA) and a physical address (PA) to a cache mechanism. A translation table is utilized to store both the address and the locking information associated with a virtual address, and this locking information is passed to the cache along with the address of the data. The cache can then lock data based on this information. Additionally, this locking information may be used to override the replacement mechanism used with the cache, thus keeping locked data in the cache. The translation table may also store translation table lock information such that entries in the translation table are locked as well. | 06-10-2010 |
Kimberly Marie Fernsler, Round Rock, TX US
Patent application number | Description | Published |
---|---|---|
20090307692 | SYSTEM AND METHOD TO DYNAMICALLY MANAGE APPLICATIONS ON A PROCESSING SYSTEM - A method and system in accordance with the present invention provides an intelligent prediction approach for populating and depopulating multiple applications at the system level across applications. The detection and management of user behavior patterns to anticipate the user's next request is provided. Further the present invention is to account for a situation to relate dynamically to user behavior and where that user behavior changes to adjust so as to more accurately set forth a desired result for a user of the present invention. The present invention in various implementations provides an intelligent prediction scheme for populating and depopulating multiple applications at the system level across a diversity of applications. | 12-10-2009 |
20090307693 | SYSTEM AND METHOD TO DYNAMICALLY MANAGE APPLICATIONS ON A PROCESSING SYSTEM - A method and system in accordance with the present invention provides an intelligent prediction approach for populating and depopulating multiple applications at the system level across applications. The detection and management of user behavior patterns to anticipate the user's next request is provided. Further the present invention is to account for a situation to relate dynamically to user behavior and where that user behavior changes to adjust so as to more accurately set forth a desired result for a user of the present invention. The present invention in various implementations provides an intelligent prediction scheme for populating and depopulating multiple applications at the system level across a diversity of applications. | 12-10-2009 |
Matthew E. Fernsler, Round Rock, TX US
Patent application number | Description | Published |
---|---|---|
20080225566 | Using eFuses to Store PLL Configuration Data - A mechanism for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the mechanism, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and serial transfer of the data in the portion of eFuses to the PLL under the reference clock. When the transfer is complete, the power up controller directs the PLL logic to load the configuration data and start. The mechanism of the present invention allows manufacturing to tailor the PLL configuration on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL from the eFuses. | 09-18-2008 |
20080229166 | Accelerating Test, Debug and Failure Analysis of a Multiprocessor Device - A mechanism for accelerating test, debug and failure analysis of a multiprocessor device is provided. With the mechanism, on-chip trace logic is utilized to receive internal signals from logic provided in modules of the multiprocessor device. The modules are preferably copies of one another such that, given the same inputs, each module should operate in the same manner and generate the same output as long as the modules are operating properly. The modules are provided with the same inputs and the internal signals of the modules are traced using an on-chip trace bus and on-chip trace logic analyzer to perform the trace. The internal signals from one module are compared against another module so as to determine if there is any discrepancy which would indicate a fault. Additional pairs of modules may be compared to pinpoint a faulty module that is the source of the fault. | 09-18-2008 |
20080288230 | STRUCTURE FOR TESTING AN OPERATION OF INTEGRATED CIRCUITRY - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes a general purpose computational resource for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is for: storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns. | 11-20-2008 |
Matthew E. Fernsler, Cedar Park, TX US
Patent application number | Description | Published |
---|---|---|
20090089636 | Method and Apparatus for Logic Built In Self Test (LBIST) Fault Detection in Multi-Core Processors - A method, system, and computer program product for identifying failures in multi-core processors, utilizing logic built-in self test (LBIST) technology. Multi-core processors, having LBIST and pseudo-random pattern generator (PRPG) circuitry, are tested. Controlled by the LBIST control logic, PRPG inputs a test pattern into scan chains within the cores of each device. A new test pattern is generated and executed during the scan shift phase of each LBIST loop. Logic output generated by each scan chain in the core is compared to other core logic output. Failures within the multi-core processors are determined by whether the logic output generated from a core, within a latch sequence, does not match the logic output of the other cores. If logic output, from a core within a latch sequence, does not match, then the latch number, loop number, and latch values are recorded as failed. | 04-02-2009 |
Matthew Earl Fernsler, Cedar Park, TX US
Patent application number | Description | Published |
---|---|---|
20090055668 | Method and Apparatus for Detecting Clock Gating Opportunities in a Pipelined Electronic Circuit Design - A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies. | 02-26-2009 |
Richard Fernsler, Annandale, VA US
Patent application number | Description | Published |
---|---|---|
20090314633 | ELECTRON BEAM ENHANCED LARGE AREA DEPOSITION SYSTEM - This invention provides a means to deposit thin films and coatings on a substrate using an electron beam generated plasma. The plasma can be used as an ion source in sputter applications, where the ions are used to liberate material from a target surface which can then condense on a substrate to form the film or coating. Alternatively, the plasma may be combined with existing deposition sources including those based on sputter or evaporation techniques. In either configuration, the plasma serves as a source of ion and radical species at the growing film surface in reactive deposition processes. The electron beam large area deposition system (EBELADS) is a new approach to the production of thin films or coatings up to and including several square meters. | 12-24-2009 |
20110308461 | Electron Beam Enhanced Nitriding System (EBENS) - An electron beam enhanced nitriding system that passes a high-energy electron beam through nitrogen gas to form a low electron temperature plasma capable of delivering nitrogen ions and radicals to a substrate to be nitrided. The substrate can be mounted on an electrode, and the substrate can be biased and heated. | 12-22-2011 |
Richard F. Fernsler, Annandale, VA US
Patent application number | Description | Published |
---|---|---|
20090032143 | ELECTRON BEAM ENHANCED NITRIDING SYSTEM - An electron beam enhanced nitriding system that passes a high-energy electron beam through nitrogen gas to form a low electron temperature plasma capable of delivering nitrogen ions and radicals to a substrate to be nitrided. The substrate can be mounted on an electrode, and the substrate can be biased and heated. | 02-05-2009 |
20110080093 | Apparatus and Method for Regulating the Output of a Plasma Electron Beam Source - An apparatus and method for controlling electron flow within a plasma to produce a controlled electron beam is provided. A plasma is formed between a cathode and an acceleration anode. A control anode is connected to the plasma and to the acceleration anode via a switch. If the switch is open, the ions from the plasma flow to the cathode and plasma electrons flow to the acceleration anode. With the acceleration anode suitably transparent and negatively biased with a DC high voltage source, the electrons flowing from the plasma are accelerated to form an electron beam. If the switch is closed, the ions still flow to the cathode but the electrons flow to the control anode rather than the acceleration anode. Consequently, the electron beam is turned off, but the plasma is unaffected. By controlling the opening and closing of the switch, a controlled pulsed electron beam can be generated. | 04-07-2011 |
20120046895 | RF Probe Technique for Determining Plasma Potential - An rf probe is placed within a plasma and an rf signal from a network analyzer for a given dc bias voltage V | 02-23-2012 |
20120084046 | LC Resonance Probe for Determining Local Plasma Density - An apparatus and method for determining plasma parameters such as plasma electron density n | 04-05-2012 |