Patent application number | Description | Published |
20110103516 | DEVICE, METHOD AND SYSTEM FOR TRANSMITTING DIGITAL BROADCASTING SIGNAL - A device for transmitting digital broadcast signal comprises: at least a first encoding unit, each of which encodes data of a sub-channel with forward error correction encoding; at least a time-domain interleaving unit, each of which receives data output from a first encoding unit and performs interleaving in time-domain on the encoded data; a first multiplexing unit, which multiplexes the interleaved data output from each of the time-domain interleaving unit into Main Service Channel (MSC) data; a second encoding unit, which performs forward error correction encoding on a second set of data to obtain Fast Information Channel (FIC) data; a differential modulating unit, which performs differential modulation on the FIC data by using a first modulation mode and on the MSC data by using a second modulation mode, wherein the modulation level of the first modulation mode is lower than that of the second modulation mode; and a frame generating and transmitting unit, which generates signal unit transmission frames by using differential-modulation symbol sequences generated by the differential modulating unit and transmitting said signal unit transmission frames. | 05-05-2011 |
20110188605 | FRAMING METHOD AND A FRAMING DEVICE OF THE COMMON INTERLEAVED FRAME - A framing method of the common interleaved frame is provided, which includes the following steps: obtaining the position information of each sub-channel in the common interleaved frame; depositing data bits in each sub-channel accordingly based on the position information of each sub-channel and the number of bits comprised in the capacity unit CU; wherein the number of bits comprised in the CU is determined by a symbol mapping mode of each sub-channel. The method can help the skilled in the art to make a CIF with the data bits at the transmitter of the T-MMB system. A framing device of the common interleaved frame is also provided in the present invention. | 08-04-2011 |
20120242935 | DIRECT ILLUMINATION TYPE BACKLIGHT MODULE, BOTTOM REFLECTOR AND LIQUID CRYSTAL DISPLAY - Embodiments of the disclosed technology provide to a direct illumination type backlight module comprising: a bottom reflecting plate with a upper reflecting surface; a plurality of diffuse reflectors provided on the upper reflecting surface of the bottom reflecting plate, each of the diffuse reflectors having at least one diffusion reflecting surface; a light source array provided on the upper reflecting surface of the bottom reflecting plate and comprising a plurality of light emitting devices, a light emitting surface of each of the light emitting devices facing the diffusion reflecting surface of at least one of the diffuse reflectors so that light from the light emitting devices is scattered upwards by the diffuse reflectors; and a diffuser provided above the light source array. In addition, a bottom reflector and a liquid crystal display are also provided. | 09-27-2012 |
20130196684 | GENERATING INDOOR RADIO MAP, LOCATING INDOOR TARGET - A method and system of generating an indoor radio map. In order to reduce the influence of multipath effect on indoor localization and improve the accuracy of indoor localization, a technique of processing data for indoor target locating and a technique of locating an indoor target based on the above technique is proposed. The method for generating an indoor radio map performs a smoothing process on the wireless signal strength measured in at least one position by a mobile node based on wireless signal strengths measured by the mobile node at adjacent positions, so as to reduce the influence of multipath effect. | 08-01-2013 |
20140119051 | LIGHT MIXING ELEMENT, LIGHT GUIDE PLATE, BACKLIGHT MODULE AND DISPLAY DEVICE - A light mixing element in a shape of a prism, and a cylinder of the prism of the light mixing element includes a first light-emitting inclined surface, a second light-emitting inclined surface, a bottom surface, a incident surface and a reflecting inclined surface; one side of the second light-emitting inclined surface is connected with one side of the first light-emitting inclined surface to form a top angle; the bottom surface is arranged opposite to the top angle; the incident surface is connected between one side of the bottom surface and the other side of the first light-emitting inclined surface; and the reflecting inclined surface is connected between the other side of the bottom surface and the other side of the second light-emitting inclined surface and arranged opposite to the incident surface and the first light-emitting inclined surface. | 05-01-2014 |
20140214592 | METHOD AND SYSTEM FOR ONLINE RECOMMENDATION - A technical solution for online recommendation. Determining, according to the first user's behaviors in the online decision process, which phase of the online decision process the first user is presented in, wherein the online decision process is divided into a plurality of phases depending on a decision conversion rate; selecting recommended items to be provided to the first user according to one or more second users' historical behavior records, wherein the one or more second users are users who are presented in one or more phases having a higher decision conversion rate than the determined phase. | 07-31-2014 |
20140368805 | DESIGN METHOD OF EXTREME ULTRAVIOLET LITHOGRAPHY PROJECTION OBJECTIVE - A design method of extreme ultraviolet lithography projection objective comprises: determining the optical design parameters of the lithography projection objective, setting the projection objective to include six lenses and an aperture diaphragm, and dividing the six lenses into the three groups according to the beam propagation direction; determining the radii and the intervals of the first and third groups, respectively; and determining the radii and the intervals of the second group of lenses according to the parameters of the foregoing two groups of lenses. The design method has the advantage of avoiding the blindness in revising and error testing of the existing structure of the conventional optical design method by calculating lens structures that meet the parameter conditions, so that light rays can be selected conveniently according to the special requirements of optical processing detection, and a mass of searches and judgments can be avoided. | 12-18-2014 |
20150273923 | DETERMINING SURVIVAL STATE OF PRINT HEAD - A solution for determining survival state of a print head. In one aspect, the cleaning behavior of a print head can be used for reflecting health status of the print head, so survival state of a print head can be determined according to cleaning behavior of the print head. Specifically, there is provided a method for determining survival state of a print head, comprising: obtaining cleaning behavior data and cumulative printing amount upon failure occurrence of print head(s) of reference printer(s) as well as cleaning behavior of a print head of a current printer; obtaining printing amount of the current printer; determining survival state of the print head of the current printer according to cleaning behavior data and cumulative printing amount upon failure occurrence of the print head(s) of the reference printer(s) as well as cleaning behavior data and printing amount of the current printer. | 10-01-2015 |
20150321469 | DETERMINING SURVIVAL STATE OF PRINT HEAD - The present invention relates to a method for determining survival state of a print head. The cleaning behavior of a print head can be used for reflecting health status of the print head, so survival state of a print head can be determined according to cleaning behavior of the print head. Specifically, a method is implemented for determining survival state of a print head, comprising: obtaining cleaning behavior data and cumulative printing amount upon failure occurrence of print head(s) of reference printer(s) as well as cleaning behavior of a print head of a current printer; obtaining printing amount of the current printer; determining survival state of the print head of the current printer according to cleaning behavior data and cumulative printing amount upon failure occurrence of the print head(s) of the reference printer(s) as well as cleaning behavior data and printing amount of the current printer. | 11-12-2015 |
20150326595 | USER LOGIN MONITORING DEVICE AND METHOD - The present invention discloses a user login monitoring device and method. The method comprises: acquiring a latest user login record list of a user, wherein each of the user login records comprises information associated with the login location of the user; determining a frequently-used login location of the user according to the user login record list, and when the number of the user login records with a same login location is not less than a first threshold, determining the login location as the frequently-used login location of the user; and marking a user login record with a different login location from the frequently-used login location as abnormal. The frequently-used login location of the user can be automatically determined without the participation of the user, and the abnormal login record can be determined and marked by using the present invention so as to facilitate the user to check or remind the user, thus the security of the user account is improved. Moreover, in some special cases, it can be determined accurately whether a user login is abnormal according to the present invention, thus the accuracy is increased and the false alarm rate is lowered. | 11-12-2015 |
20150333297 | ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY APPARATUS - Disclosed is an organic electroluminescent display device, a manufacturing method thereof and a display apparatus including the same. The organic electroluminescent display device includes an substrate comprising a main material film layer, and a first phase difference film layer, a water and oxygen-proof film layer and a polarizing film layer provided to stack each other; an organic electroluminescent pixel array provided on the substrate, the organic electroluminescent pixel array may emitting visible light capable of passing through the substrate; and a package substrate or a package thin film cladding outside of the organic electroluminescent pixel array. The first phase difference film layer is located at a side of the polarizing film layer near the organic electroluminescent pixel array. The substrate may have the function of anti-reflection as well as the good performance of water-proof and oxygen-proof. In this way, the OLED device of bottom-emission type provided on the substrate may leave out double film-applying process for applying the circular polarizing filter and the water and oxygen-proof film layer, and avoid the problems of thickening the thickness of a flexible device and bending brought about by the double film-applying. | 11-19-2015 |
Patent application number | Description | Published |
20110031633 | AIR CHANNEL INTERCONNECTS FOR 3-D INTEGRATION - A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof. In addition, the 3D chip stack structure further includes one or more openings in a peripheral region of the chip stack structure that lead into and out of the air channel interconnect network, so that air can flow into and out of the air channel interconnect network through the one or more openings to remove heat from the chip stack structure. | 02-10-2011 |
20110083786 | ADAPTIVE CHUCK FOR PLANAR BONDING BETWEEN SUBSTRATES - An electrostatic chuck includes an array of independently biased conductive chuck elements, an array of sensor-conductor assemblies, and/or a combination of an array of sensor-conductor assemblies and at least one motorized chuck. Conductive chuck elements, either standing alone or embedded in a sensor-conductor assembly, are independently biased electrostatically to compensate for bowing and/or warping of a substrate thereupon so that the substrate can be bonded with a planar surface. A single electrostatic chuck can be employed to reduce the bowing and warping of one of the two substrates to be bonded, or two electrostatic chucks can be employed to minimize the bowing and warping of two substrates to be bonded. | 04-14-2011 |
20120043814 | SOLAR CELL AND BATTERY 3D INTEGRATION - An integrated photovoltaic cell and battery device, a method of manufacturing the same and a photovoltaic power system incorporating the integrated photovoltaic cell and battery device. The integrated photovoltaic cell and battery device includes a photovoltaic cell, a battery, and interconnects providing three-dimensional integration of the photovoltaic cell and the battery into an integrated device for capturing and storing solar energy. Also provided is a design structure readable by a machine to simulate, design, or manufacture the above integrated photovoltaic cell and battery device. | 02-23-2012 |
20120268985 | RESONANCE NANOELECTROMECHANICAL SYSTEMS - Systems and methods for operating a nanometer-scale cantilever beam with a gate electrode. An example system includes a drive circuit coupled to the gate electrode where a drive signal from the circuit may cause the beam to oscillate at or near the beam's resonance frequency. The drive signal includes an AC component, and may include a DC component as well. An alternative example system includes a nanometer-scale cantilever beam, where the beam oscillates to contact a plurality of drain regions. | 10-25-2012 |
20120286377 | Nanoelectromechanical Structures Exhibiting Tensile Stress And Techniques For Fabrication Thereof - Improved nano-electromechanical system devices and structures and systems and techniques for their fabrication. In one embodiment, a structure comprises an underlying substrate separated from first and second anchor points by first and second insulating support points, respectively. The first and second anchor points are joined by a beam. First and second deposition regions overlie the first and second anchor points, respectively, and the first and second deposition regions exert compression on the first and second anchor points, respectively. The compression on the first and second anchor points causes opposing forces on the beam, subjecting the beam to a tensile stress. The first and second deposition regions suitably exhibit an internal tensile stress having an achievable maximum varying with their thickness, so that the tensile stress exerted on the beam depends at least on part on the thickness of the first and second deposition regions. | 11-15-2012 |
20120318649 | Silicide Micromechanical Device and Methods to Fabricate Same - A method is disclosed to fabricate an electro-mechanical device such as a MEMS or NEMS switch. The method includes providing a silicon layer disposed over an insulating layer that is disposed on a silicon substrate; releasing a portion of the silicon layer from the insulating layer so that it is at least partially suspended over a cavity in the insulating layer; depositing a metal (e.g., Pt) on at least one surface of at least the released portion of the silicon layer and, using a thermal process, fully siliciding at least the released portion of the silicon layer using the deposited metal. The method eliminates silicide-induced stress to the released Si member, as the entire Si member is silicided. Furthermore no conventional wet chemical etch is used after forming the fully silicided material thereby reducing a possibility of causing corrosion of the silicide and an increase in stiction. | 12-20-2012 |
20130020183 | Silicide Micromechanical Device and Methods to Fabricate Same - A miniaturized electro-mechanical switch includes a moveable portion having a contact configured to make, when the switch is actuated, an electrical connection between two stationary points. At least the contact is composed of a fully silicided material. A structure includes a silicon layer formed over an insulator layer and a micromechanical switch formed at least partially within the silicon layer. The micromechanical switch has a conductive structure, and where at least electrically contacting portions of the conductive structure are comprised of fully silicided material. | 01-24-2013 |
20130146948 | MICROMECHANICAL DEVICE AND METHODS TO FABRICATE SAME USING HARD MASK RESISTANT TO STRUCTURE RELEASE ETCH - A structure includes a silicon layer disposed on a buried oxide layer that is disposed on a substrate; at least one transistor device formed on or in the silicon layer, the at least one transistor having metallization; a released region of the silicon layer disposed over a cavity in the buried oxide layer; a back end of line (BEOL) dielectric film stack overlying the silicon layer and the at least one transistor device; a nitride layer overlying the BEOL dielectric film stack; a hard mask formed as a layer of hafnium oxide overlying the nitride layer; and an opening made through the layer of hafnium oxide, the layer of nitride and the BEOL dielectric film stack to expose the released region of the silicon layer disposed over the cavity in the buried oxide layer. The hard mask protects the underlying material during a MEMS/NEMS HF vapor release procedure. | 06-13-2013 |
20130183553 | BATTERY WITH SELF-PROGRAMMING FUSE - A useful lifetime of an energy storage device can be extended by providing a series connection of a battery cell and an self-programming fuse. A plurality of series connections of a battery cell and an self-programming fuse can then be connected in a parallel connection to expand the energy storage capacity of the energy storage device. Each self-programming fuse can be a strip of a metal semiconductor alloy material, which electromigrates when a battery cell is electrically shorted and causes increases in the amount of electrical current therethrough. Thus, each self-programming fuse is a self-programming circuit that opens once the battery cell within the same series connection is shorted. | 07-18-2013 |
20140000712 | NIOBIUM THIN FILM STRESS RELIEVING LAYER FOR THIN-FILM SOLAR CELLS | 01-02-2014 |
20140103422 | STRUCTURE FOR MEMS TRANSISTORS ON FAR BACK END OF LINE - A MEMS transistor for a FBEOL level of a CMOS integrated circuit is disclosed. The MEMS transistor includes a cavity within the integrated circuit. A MEMS cantilever switch having two ends is disposed within the cavity and anchored at least at one of the two ends. A gate and a drain are in a sidewall of the cavity, and are separated from the MEMS cantilever switch by a gap. In response to a voltage applied to the gate, the MEMS cantilever switch moves across the gap in a direction parallel to the plane of the FBEOL level of the CMOS integrated circuit into electrical contact with the drain to permit a current to flow between the source and the drain. Methods for fabricating the MEMS transistor are also disclosed. In accordance with the methods, a MEMS cantilever switch, a gate, and a drain are constructed on a far back end of line (FBEOL) level of a CMOS integrated circuit in a plane parallel to the FBEOL level. The MEMS cantilever switch is separated from the gate and the drain by a sacrificial material, which is ultimately removed to release the MEMS cantilever switch and to provide a gap between the MEMS cantilever switch and the gate and the drain. | 04-17-2014 |
20140106552 | Method Of Fabricating MEMS Transistors On Far Back End Of Line - A MEMS transistor for a FBEOL level of a CMOS integrated circuit is disclosed. The MEMS transistor includes a cavity within the integrated circuit. A MEMS cantilever switch having two ends is disposed within the cavity and anchored at least at one of the two ends. A gate and a drain are in a sidewall of the cavity, and are separated from the MEMS cantilever switch by a gap. In response to a voltage applied to the gate, the MEMS cantilever switch moves across the gap in a direction parallel to the plane of the FBEOL level of the CMOS integrated circuit into electrical contact with the drain to permit a current to flow between the source and the drain. Methods for fabricating the MEMS transistor are also disclosed. In accordance with the methods, a MEMS cantilever switch, a gate, and a drain are constructed on a far back end of line (FBEOL) level of a CMOS integrated circuit in a plane parallel to the FBEOL level. The MEMS cantilever switch is separated from the gate and the drain by a sacrificial material, which is ultimately removed to release the MEMS cantilever switch and to provide a gap between the MEMS cantilever switch and the gate and the drain. | 04-17-2014 |
20140117498 | Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process - In one aspect, a memory cell capacitor is provided. The memory cell capacitor includes a silicon wafer; at least one trench in the silicon wafer; a silicide within the trench that serves as a bottom electrode of the memory cell capacitor, wherein a contact resistance between the bottom electrode and the silicon wafer is from about 1×10 | 05-01-2014 |
20140120687 | Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process - In one aspect, a method of fabricating a memory cell capacitor includes the following steps. At least one trench is formed in a silicon wafer. A thin layer of metal is deposited onto the silicon wafer, lining the trench, using a conformal deposition process under conditions sufficient to cause at least a portion of the metal to self-diffuse into portions of the silicon wafer exposed within the trench forming a metal-semiconductor alloy. The metal is removed from the silicon wafer selective to the metal-semiconductor alloy such that the metal-semiconductor alloy remains. The silicon wafer is annealed to react the metal-semiconductor alloy with the silicon wafer to form a silicide, wherein the silicide serves as a bottom electrode of the memory cell capacitor. A dielectric is deposited into the trench covering the bottom electrode. A top electrode is formed in the trench separated from the bottom electrode by the dielectric. | 05-01-2014 |
20140151786 | NON-VOLATILE GRAPHENE NANOMECHANICAL SWITCH - Non-volatile switches and methods for making the same include a gate material formed in a recess of a substrate; a flexible conductive element disposed above the gate material, separated from the gate material by a gap, where the flexible conductive element is supported on at least two points across the gap, and where a voltage above a gate threshold voltage causes a deformation in the flexible conductive element such that the flexible conductive element comes into contact with a drain in the substrate, thereby closing a circuit between the drain and a source terminal. The gap separating the flexible conductive element and the gate material is sized to create a negative threshold voltage at the gate material for opening the circuit. | 06-05-2014 |
20140154851 | NON-VOLATILE GRAPHENE NANOMECHANICAL SWITCH - Methods for making non-volatile switches include depositing gate material in a recess of a substrate; depositing drain metal in a recess of the gate material; planarizing the gate material, drain metal, and substrate; forming sidewalls by depositing material on the substrate around the gate material; forming a flexible conductive element between the sidewalls to establish a gap between the flexible conductive element and the gate material, such that the gap separating the flexible conductive element and the gate material is sized to create a negative threshold voltage at the gate material for opening a circuit; and forming a source terminal in electrical contact with the flexible conductive element. | 06-05-2014 |
20140203360 | REDUCING CONTACT RESISTANCE BY DIRECT SELF-ASSEMBLING - As stated above, methods of forming a source/drain contact for a transistor are disclosed. In one embodiment, a transistor is formed on a semiconductor-on-insulator (SOI) substrate, which includes a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate. This forming can include forming a gate and a source/drain region. A hardmask can then be formed over the transistor and a self-assembling (DSA) polymer can be directed to cover a portion of the source/drain region. A set of trenches can be formed through the hardmask and into the source/drain region using the DSA polymer as a mask. Then the polymer and the hardmask can be stripped, leaving the trenched source/drain region. | 07-24-2014 |
20140264482 | CARBON-DOPED CAP FOR A RAISED ACTIVE SEMICONDUCTOR REGION - After formation of a disposable gate structure, a raised active semiconductor region includes a vertical stack, from bottom to top, of an electrical-dopant-doped semiconductor material portion and a carbon-doped semiconductor material portion. A planarization dielectric layer is deposited over the raised active semiconductor region, and the disposable gate structure is replaced with a replacement gate structure. A contact via cavity is formed through the planarization dielectric material layer by an anisotropic etch process that employs a fluorocarbon gas as an etchant. The carbon in the carbon-doped semiconductor material portion retards the anisotropic etch process, and the carbon-doped semiconductor material portion functions as a stopping layer for the anisotropic etch process, thereby making the depth of the contact via cavity less dependent on variations on the thickness of the planarization dielectric layer or pattern factors. | 09-18-2014 |
20140312249 | COLORIMETRIC RADIATION DOSIMETRY BASED ON FUNCTIONAL POLYMER AND NANOPARTICLE HYBRID - A method for colorimetric radiation dosimetry includes subjecting an aggregate including a polymeric matrix having uniformly dispersed nanoparticles therein to radiation. The aggregate is soaked in a solution selected to dissolve decomposed pieces of the polymeric matrix to release into the solution nanoparticles from the decomposed pieces. Color of the solution is compared to a reference to determine a dose of radiation based on number of liberated nanoparticles. | 10-23-2014 |
20140315316 | COLORIMETRIC RADIATION DOSIMETRY BASED ON FUNCTIONAL POLYMER AND NANOPARTICLE HYBRID - A method for colorimetric radiation dosimetry includes subjecting an aggregate including a polymeric matrix having uniformly dispersed nanoparticles therein to radiation. The aggregate is soaked in a solution selected to dissolve decomposed pieces of the polymeric matrix to release into the solution nanoparticles from the decomposed pieces. Color of the solution is compared to a reference to determine a dose of radiation based on number of liberated nanoparticles. | 10-23-2014 |
20140326047 | Techniques for Fabricating Janus Sensors - Electromechanical sensors that employ Janus micro/nano-components and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating an electromechanical sensor includes the following steps. A back gate is formed on a substrate. A gate dielectric is deposited over the back gate. An intermediate layer is formed on the back gate having a micro-fluidic channel formed therein. Top electrodes are formed above the micro-fluidic channel. One or more Janus components are placed in the micro-fluidic channel, wherein each of the Janus components has a first portion having an electrically conductive material and a second portion having an electrically insulating material. The micro-fluidic channel is filled with a fluid. The electrically insulating material has a negative surface charge at a pH of the fluid and an isoelectric point at a pH less than the pH of the fluid. | 11-06-2014 |
20140326613 | Techniques for Fabricating Janus Sensors - Electromechanical sensors that employ Janus micro/nano-components and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating an electromechanical sensor includes the following steps. A back gate is formed on a substrate. A gate dielectric is deposited over the back gate. An intermediate layer is formed on the back gate having a micro-fluidic channel formed therein. Top electrodes are formed above the micro-fluidic channel. One or more Janus components are placed in the micro-fluidic channel, wherein each of the Janus components has a first portion having an electrically conductive material and a second portion having an electrically insulating material. The micro-fluidic channel is filled with a fluid. The electrically insulating material has a negative surface charge at a pH of the fluid and an isoelectric point at a pH less than the pH of the fluid. | 11-06-2014 |
20140345687 | NIOBIUM THIN FILM STRESS RELIEVING LAYER FOR THIN-FILM SOLAR CELLS - A photovoltaic device includes a thermal stress relieving layer on top of a substrate; a back ohmic contact on the thermal stress relieving layer; and a p-type semiconductor photon absorber layer on the back ohmic contact. The back ohmic contact comprises a metallic compound of the sacrificial back electrode metal layer and the absorber layer, in combination with the thermal stress relieving layer. The thermal stress relieving layer has a substantially similar thermal expansion coefficient with respect to the substrate and the absorber layer and a lower Young's modulus with respect to the sacrificial back electrode metal layer. | 11-27-2014 |
20140353589 | REPLACEMENT GATE SELF-ALIGNED CARBON NANOSTRUCTURE TRANSISTOR - A self-aligned carbon nanostructure transistor is formed by a method that includes providing a material stack including a gate dielectric material having a dielectric constant of greater than silicon oxide and a sacrificial gate material. Next, a carbon nanostructure is formed on an exposed surface of the gate dielectric material. After forming the carbon nanostructure, metal semiconductor alloy portions are formed self-aligned to the material stack. The sacrificial gate material is then replaced with a conductive metal. | 12-04-2014 |
20140353590 | REPLACEMENT GATE SELF-ALIGNED CARBON NANOSTRUCTURE TRANSISTOR - A self-aligned carbon nanostructure transistor is formed by a method that includes providing a material stack including a gate dielectric material having a dielectric constant of greater than silicon oxide and a sacrificial gate material. Next, a carbon nanostructure is formed on an exposed surface of the gate dielectric material. After forming the carbon nanostructure, metal semiconductor alloy portions are formed self-aligned to the material stack. The sacrificial gate material is then replaced with a conductive metal. | 12-04-2014 |
20150014755 | JANUS COMPLEMENTARY MEMS TRANSISTORS AND CIRCUITS - A method of fabricating an electromechanical device includes the following steps. A first and a second back gate are formed over a substrate. An etch stop layer is formed covering the first and second back gates. Electrodes are formed over the first and second back gates, wherein the electrodes include one or more gate, source, and drain electrodes, wherein gaps are present between the source and drain electrodes. One or more Janus components are placed the gaps, each of which includes a first portion having an electrically conductive material and a second portion having an electrically insulating material, and wherein i) the first or second portion of the Janus components placed in a first one of the gaps has a fixed positive surface charge and ii) the first or second portion of the Janus components placed in a second one of the gaps has a fixed negative surface charge. | 01-15-2015 |
20150064897 | PROCESS VARIABILITY TOLERANT HARD MASK FOR REPLACEMENT METAL GATE FINFET DEVICES - Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall. | 03-05-2015 |
20150285920 | COLORIMETRIC RADIATION DOSIMETRY BASED ON FUNCTIONAL POLYMER AND NANOPARTICLE HYBRID - A method for colorimetric radiation dosimetry includes subjecting an aggregate including a polymeric matrix having uniformly dispersed nanoparticles therein to radiation. The aggregate is soaked in a solution selected to dissolve decomposed pieces of the polymeric matrix to release into the solution nanoparticles from the decomposed pieces. Color of the solution is compared to a reference to determine a dose of radiation based on number of liberated nanoparticles. | 10-08-2015 |
Patent application number | Description | Published |
20110037128 | METHOD AND STRUCTURE FOR IMPROVING UNIFORMITY OF PASSIVE DEVICES IN METAL GATE TECHNOLOGY - Method of forming a semiconductor device which includes the steps of obtaining a semiconductor substrate having a logic region and an STI region; sequentially depositing layers of high K material, metal gate, first silicon and hardmask; removing the hardmask and first silicon layers from the logic region; applying a second layer of silicon on the semiconductor substrate such that the logic region has layers of high K material, metal gate and second silicon and the STI region has layers of high K material, metal gate, first silicon, hardmask and second silicon. There may also be a second hardmask layer between the metal gate layer and the first silicon layer in the STI region. There may also be a hardmask layer between the metal gate layer and the first silicon layer in the STI region but no hardmask layer between the first and second layers of silicon in the STI region. | 02-17-2011 |
20110233785 | BACKSIDE DUMMY PLUGS FOR 3D INTEGRATION - A semiconductor structure includes backside dummy plugs embedded in a substrate. The backside dummy plugs can be a conductive structure that enhances vertical thermal conductivity of the semiconductor structure and provides electrical decoupling of signals in through-substrate vias (TSVs) in the substrate. The backside dummy plug can include a cavity to accommodate volume changes in other components in the substrate, thereby alleviating mechanical stress in the substrate during thermal cycling and operation of the semiconductor chip. The backside dummy plug including the cavity can be composed of an insulator material or a conductive material. The inventive structures can be employed to form three-dimensional structures having vertical chip integration, in which inter-wafer thermal conductivity is enhanced, cross-talk between signals through TSVs is reduced, and/or mechanical stress to the TSVs is reduced. | 09-29-2011 |
20110241185 | SIGNAL SHIELDING THROUGH-SUBSTRATE VIAS FOR 3D INTEGRATION - A shielded through-substrate via (TSV) structure includes a first through-substrate via configured to transmit a signal at least from a top surface of a semiconductor device layer in a substrate to a bottommost surface of the substrate. The shielded TSV structure includes at least one second TSV located on the outside of the first TSV and configured to laterally shield the first TSV from external electrical signals. The at least one second TSV can be a unitary cylindrical structure including the first TSV therein, or a plurality of discrete structures configured to laterally shield the first TSV with gaps thereamongst. The at least one second TSV can include a conductive material that is different from the material of the substrate, or the at least one TSV can include a doped semiconductor material that is derived from the semiconductor material within the substrate. | 10-06-2011 |
20110248396 | BOW-BALANCED 3D CHIP STACKING - A first set of semiconductor substrates includes semiconductor chips having bonding pads arranged in a primary pattern. A second set of semiconductor substrates includes semiconductor chips having bonding pads arranged in a mirror-image pattern. A first semiconductor substrate from the first set is bonded to a second semiconductor substrate from the second set such that each bonding pads is bonded to a mirror-image bonding pad. Additional substrates are bonded sequentially such that the bonded structure includes an even number of semiconductor substrates of which one half have bonding pads of the primary pattern and are bonded to the side of the first semiconductor substrate, while the other half have bonding pads of the mirror-image pattern and are bonded to the side of the second semiconductor substrate. The mirror-image patterns of the bonding pads enable maximal cancellation of wafer bow. | 10-13-2011 |
20110278063 | Precise-Aligned Lock-and-Key Bonding Structures - Copper (Cu)-to-Cu bonding techniques are provided. In one aspect, a bonding method is provided. The method includes the following steps. A first bonding structure is provided having at least one copper pad embedded in a first insulator and at least one via in the first insulator over the copper pad, wherein the via has tapered sidewalls. A second bonding structure is provided having at least one copper stud embedded in a second insulator, wherein a portion of the copper stud is exposed for bonding and has a domed shape. The first bonding structure is bonded to the second bonding structure by way of a copper-to-copper bonding between the copper pad and the copper stud, wherein the via and the copper stud fit together like a lock-and-key. A bonded structure is also provided. | 11-17-2011 |
20110278740 | SCALABLE TRANSFER-JOIN BONDING LOCK-AND-KEY STRUCTURES - Scalable transfer-join bonding techniques are provided. In one aspect, a transfer-join bonding method is provided. The method includes the following steps. A first bonding structure is provided having at least one metal pad embedded in an insulator and at least one via in the insulator over the metal pad. The via has tapered sidewalls. A second bonding structure is provided having at least one copper stud tapered to complement the tapered sidewalls of the via, such that the via and the copper stud fit together like a lock-and-key. The first bonding structure is bonded to the second bonding structure by way of a metal-to-metal bonding between the metal pad and the copper stud. A transfer join bonded structure is also provided. | 11-17-2011 |
20120181508 | Graphene Devices and Silicon Field Effect Transistors in 3D Hybrid Integrated Circuits - A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer. | 07-19-2012 |
20120278038 | ESTIMATING MONTHLY HEATING OIL CONSUMPTION FROM FISCAL YEAR OIL CONSUMPTION DATA USING MULTIPLE REGRESSION AND HEATING DEGREE DAY DENSITY FUNCTION - Estimating monthly heating oil consumption of a building that uses heating oil and non-oil source of energy, may include separating by applying statistical models, yearly consumption of oil data associated with the building into base load oil consumption and space heating oil consumption. The separating may also include determining monthly base load oil consumption associated with the building. Monthly space heating consumption of oil may be estimated by applying a heating degree day density function to the space heating oil consumption. The monthly space heating consumption may be aggregated with the monthly base load oil consumption to estimate the monthly heating oil consumption. | 11-01-2012 |
20120292702 | Graphene Devices and Silicon Field Effect Transistors in 3D Hybrid Integrated Circuits - A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer. | 11-22-2012 |
20120312452 | ADAPTIVE CHUCK FOR PLANAR BONDING BETWEEN SUBSTRATES - An electrostatic chuck includes an array of independently biased conductive chuck elements, an array of sensor-conductor assemblies, and/or a combination of an array of sensor-conductor assemblies and at least one motorized chuck. Conductive chuck elements, either standing alone or embedded in a sensor-conductor assembly, are independently biased electrostatically to compensate for bowing and/or warping of a substrate thereupon so that the substrate can be bonded with a planar surface. A single electrostatic chuck can be employed to reduce the bowing and warping of one of the two substrates to be bonded, or two electrostatic chucks can be employed to minimize the bowing and warping of two substrates to be bonded. | 12-13-2012 |
20140061901 | Precise-Aligned Lock-And-Key Bonding Structures - Copper (Cu)-to-Cu bonding techniques are provided. In one aspect, a bonding method is provided. The method includes the following steps. A first bonding structure is provided having at least one copper pad embedded in a first insulator and at least one via in the first insulator over the copper pad, wherein the via has tapered sidewalls. A second bonding structure is provided having at least one copper stud embedded in a second insulator, wherein a portion of the copper stud is exposed for bonding and has a domed shape. The first bonding structure is bonded to the second bonding structure by way of a copper-to-copper bonding between the copper pad and the copper stud, wherein the via and the copper stud fit together like a lock-and-key. A bonded structure is also provided. | 03-06-2014 |
Patent application number | Description | Published |
20100047964 | 3D INTEGRATED CIRCUIT DEVICE FABRICATION USING INTERFACE WAFER AS PERMANENT CARRIER - A method is provided for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer. Also provided is a tangible computer readable medium encoded with a program that comprises instructions for performing such a method. | 02-25-2010 |
20100314711 | 3D INTEGRATED CIRCUIT DEVICE HAVING LOWER-COST ACTIVE CIRCUITRY LAYERS STACKED BEFORE HIGHER-COST ACTIVE CIRCUITRY LAYER - A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure. | 12-16-2010 |
20120092771 | EMBEDDED VERTICAL OPTICAL GRATING FOR HETEROGENEOUS INTEGRATION - An embedded vertical optical grating, a semiconductor device including the embedded vertical optical grating and a method for forming the same. The method for forming the embedded optical grating within a substrate includes depositing a hard mask layer on the substrate, patterning at least one opening within the hard mask layer, vertically etching a plurality of scallops within the substrate corresponding to the at least one opening within the hard mask layer, removing the hard mask layer, and forming an oxide layer within the plurality of scallops to form the embedded vertical optical grating. | 04-19-2012 |
20120299200 | 3D INTEGRATED CIRCUIT DEVICE HAVING LOWER-COST ACTIVE CIRCUITRY LAYERS STACKED BEFORE HIGHER-COST ACTIVE CIRCUITRY LAYER - A 3D integrated circuit structure is provided. The 3D integrated circuit structure includes an interface wafer including a first wiring layer, a first active circuitry layer including active circuitry, and a wafer including active circuitry. The first active circuitry layer is bonded face down to the interface wafer, and the wafer is bonded face down to the first active circuitry layer. The first active circuitry layer is lower-cost than the wafer. | 11-29-2012 |
20120309127 | METHOD FOR FABRICATING 3D INTEGRATED CIRCUIT DEVICE USING INTERFACE WAFER AS PERMANENT CARRIER - A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a | 12-06-2012 |
20130189813 | COMPUTER READABLE MEDIUM ENCODED WITH A PROGRAM FOR FABRICATING A 3D INTEGRATED CIRCUIT STRUCTURE - A computer readable medium encoded with a program for fabricating a 3D integrated circuit structure is provided. The program includes instructions for performing the following process. A first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. | 07-25-2013 |
20150024548 | COMPUTER READABLE MEDIUM ENCODED WITH A PROGRAM FOR FABRICATING 3D INTEGRATED CIRCUIT DEVICE USING INTERFACE WAFER AS PERMANENT CARRIER - A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer. | 01-22-2015 |