| Patent application number | Description | Published |
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| 20090325922 | TURFGRASS FUNGICIDE FORMULATION WITH PIGMENT - Oil-in-water fungicidal formulations are prepared having pigment dispersed therein, the pigment being stable within the oil-in-water emulsion as a result of the addition of suitable silicone surfactants and suitable emulsifiers. The formulations can be prepared either as a 2-pack formulation or as a single formulation. In the case of the single formulation polyethylene glycol is also added. In either case, the formulations show a synergistic effect through the addition of the pigment, the resulting formulations having an increased efficacy. Further, the formulations show a synergistic effect when mixed with conventional chemical fungicides, both being added in reduced amounts compared to recommended rates. | 12-31-2009 |
| 20100016447 | SPRAY OIL AND METHOD OF USE THEREOF FOR CONTROLLING TURFGRASS PESTS - A paraffinic spray oil and a method of using the spray oil for controlling turfgrass pests is disclosed. The spray oil comprises paraffinic oil and a quick break emulsifier, which is formulated as an oil-in-water (O/W) emulsion for use. The paraffinic oil and emulsifier are present in a weight ratio ranging from about 95:5 to about 99.95:0.05, and preferably from about 98.5:1.5 to about 99.9:0.1. When applied to turfgrass, the O/W emulsion quickly releases the oil phase upon application to the turfgrass to contact pests thereon. When provided at sufficient paraffinic oil dosages, generally at least about 0.5 gal oil/acre and preferably in the range of about 0.5 gal/acre to about 60 gal/acre, the spray oil is effective in controlling a variety of turfgrass pests, particularly insect and fungal pests, with little or no phytotoxic effects. Further, use of the spray oil as indicated for controlling turfgrass pests also enhances the growth of turfgrass. | 01-21-2010 |
| 20120071368 | Drilling Fluid for Enhanced Rate of Penetration - A drilling fluid is provided which results in an enhanced rate of penetration, and more particularly, a drilling mud composition is provided with a reduced ester content which maintains an enhanced rate of penetration. | 03-22-2012 |
| 20120080195 | Drilling Composition, Process for its Preparation, and Applications Thereof - The present invention relates to a drilling composition comprising: I) an organic phase comprising components: i. from about 20 wt. % to about 99.999 wt. %, based on the total weight of components i. and ii., of at least one linear or branched, cyclic or non-cyclic, saturated hydrocarbon; ii. from about 0.001 wt. % to about 25 wt. %, based on the total weight of components i. and ii., of at least one ester; II) from 0 to about 50 wt. %, based on the total weight of the composition, of water or aqueous phase; III) from 0 to about 60 wt. %, based on the total weight of the composition, of at least one additive, wherein the sum of the weight components I) to III) is 100 wt. %, to a process for preparation of a drilling composition, to uses of a drilling composition, to a drilling system, to a process for making a borehole, to a process for conveying cuttings, to a process for treating a drill head, to a process for production of at least one of oil and gas. | 04-05-2012 |
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| 20100072979 | METHOD FOR TESTING A VARIABLE DIGITAL DELAY LINE AND A DEVICE HAVING VARIABLE DIGITAL DELAY LINE TESTING CAPABILITIES - A device and a method for testing a variable digital delay line that includes multiple taps. The method includes providing, an input signal to the variable digital delay line and finding, for each tap out of a group of tested taps of the variable digital delay line, a variable delay unit configuration that provides a delay that is closest to a delay introduced by the tap; wherein the variable digital delay line and the variable delay unit belong to the same integrated circuit. | 03-25-2010 |
| 20110121818 | INTEGRATED CIRCUIT DIE, AN INTEGRATED CIRCUIT PACKAGE AND A METHOD FOR CONNECTING AN INTEGRATED CIRCUIT DIE TO AN EXTERNAL DEVICE - An integrated circuit die comprises an electronic circuit and one or more output ports for outputting signals from the die via an external impedance, to a load, external from the die. The output port is connected to the electronic circuit. The die is further provided with an on-die sampling oscilloscope circuit connected to the output port, for measuring a waveform of the outputted signals. | 05-26-2011 |
| 20120038367 | CONNECTION QUALITY VERIFICATION FOR INTEGRATED CIRCUIT TEST - An integrated circuit device comprising a semiconductor die contained in a package. The integrated circuit device includes one or more internal connection verification modules for asserting a poor connection signal for the test apparatus in response to a voltage difference between a voltage at a corresponding internal power supply node and a reference voltage, the voltage difference being indicative of a poor connection of power supply to one of power supply terminals on the package. The test apparatus can include an indicator or a sorting element for rejecting or accepting the integrated circuit device in response to logic signals indicative of the presence or absence of a defect accompanied by non-assertion of the poor connection signal, and for processing the integrated circuit device distinctively in response to assertion of the poor connection signal. | 02-16-2012 |
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| 20080224684 | Device and Method for Compensating for Voltage Drops - A device that includes a voltage supply unit and an integrated circuit, the device is characterized by including a voltage sampling circuit adapted to sample voltage levels at multiple sampling points within the integrated circuit, to provide multiple sampled voltages, wherein the multiple sampled voltages reflect the voltage drops; and wherein the voltage supply unit is adapted to adjust a supply voltage provided to the integrated circuit in response to at least one sampled voltage. A method for voltage drop compensation; the method includes providing a supply voltage to an integrated circuit; the method is characterized by sampling voltage levels at multiple sampling points within the integrated circuit, to provide multiple sampled voltages, wherein the multiple sampled voltages reflect the voltage drops; and adjusting a supply voltage provided to the integrated circuit in response to at least one sampled voltage. | 09-18-2008 |
| 20090134883 | DEVICE AND METHOD FOR TESTING A NOISE IMMUNITY CHARACTERISTIC OF ANALOG CIRCUITS - A method for testing a noise immunity characteristic of an analog circuit of an integrated circuit. The device includes: an analog circuit, an internal stable reference signal source, an internal power supply module connected to the analog circuit and adapted to receive, via first input, a high level voltage supply, the device is characterized by including: a signal modulator that is adapted to provide, during a test period, a noisy signal to a second input of the internal power supply module; whereas the internal power supply module is adapted to output a noisy power supply to the analog circuit, in response to the noisy signal; whereas device is adapted to output an output signal representative of a noise immunity characteristic of the analog circuit. The method includes: providing a high level supply voltage to a first input of an internal power supply module of an integrated circuit and receiving signals from the integrated circuit representative of the performance of the analog circuit. The method is characterized by providing, during a test period, a noisy signal to a second input of the internal power supply module; providing a noisy supply voltage to the analog circuit, by the internal power supply module, in response to the noisy signal; and evaluating a noise immunity characteristic of the analog circuit in response to the received signals. | 05-28-2009 |
| 20100001755 | METHOD FOR TESTING NOISE IMMUNITY OF AN INTEGRATED CIRCUIT AND A DEVICE HAVING NOISE IMMUNITY TESTING CAPABILITIES - A method for testing a noise immunity of an integrated circuit; the method includes: determining a value of a power supply noise regardless of a relationship between the power supply noise value and a phase sensitive signal edge position resulting from an introduction of the power supply noise; receiving, by the integrated circuit, a phase sensitive signal; introducing jitter to the phase sensitive signal by a circuit adapted to generate a substantially continuous range of power supply noise such as to alter edges position of the phase sensitive signal; providing the jittered phase sensitive signal to at least one tested component of the integrated circuit; and evaluating at least one output signal generated by the at least tested component to determine the noise immunity of the integrated circuit. | 01-07-2010 |
| 20100225346 | DEVICE AND METHOD FOR EVALUATING ELECTROSTATIC DISCHARGE PROTECTION CAPABILITIES - A device and a method for evaluating ESD protection capabilities of an integrated circuit, the method includes: connecting multiple test probe to multiple integrated circuit testing points. The method is characterized by repeating the stages of: (i) charging a discharge capacitor to an ESD protection circuit triggering voltage level; (ii) connecting the discharge capacitor to the integrated circuit during a testing period such as to cause the discharge capacitor to interact with the integrated circuit; (iii) measuring at least one signal of the integrated circuit, during at least a portion of the testing period; and (iv) determining at least one ESD protection characteristic of the integrated circuit in response to the at least one signal. | 09-09-2010 |
