| Patent application number | Description | Published |
|---|
| 20090222927 | Concealment of Information in Electronic Design Automation - In one exemplary embodiment disclosed herein, an electronic design automation tool may receive information related to electronic design automation that contains secured information, such as physically secured information, and annotations to indicate the secured portions of the information. Upon receiving such information, the electronic design automation tool may identify those portions of the information comprising secured information related to electronic design automation, and unlock the secured information for processing. The electronic design automation tool may process at least some of the secured electronic design automation information without revealing that secured information to unauthorized persons, tools, systems, or otherwise compromising the protection of that secured information. That is, the design automation tool may process the secured electronic design automation information so that the secured information is concealed both while it is being processed and by the output information generated from processing the secured information. | 09-03-2009 |
| 20090235213 | Layout-Versus-Schematic Analysis For Symmetric Circuits - Techniques for reducing the complexity of Electronic Design Automation Layout-Versus-Schematic algorithms to approximately O(n) for graphs without type-3 symmetries. | 09-17-2009 |
| 20100023897 | Property-Based Classification In Electronic Design Automation - One or more properties can be associated with a design object in a microdevice design. These properties then can be used to classify relationships in a circuit design, such as a layout circuit design. In some implementations, the various relationships can be classified based upon the similarity or dissimilarity of the associated property values. | 01-28-2010 |
| 20100023905 | Critical Area Deterministic Sampling - A layout design for a portion of a microdevice design is partitioned into sections or “bins.” Next, a critical area value is estimated for one or more of the bins. One or more of these estimated bins is then selected for a more detailed analysis. After the estimated bins have been selected, a detailed critical area analysis of the selected bins is performed. Once the actual critical area for each of the estimated bins has been determined, the actual critical areas for selected estimated bins are correlated with those bin's corresponding estimated values. By correlating the actual critical areas of selected estimated bin to those bin's corresponding estimated values, a mapping function can be determined. After the mapping function has been determined, it is applied to the estimated values for each of the remaining bins of the layout design (i.e., the bins for which an actual critical area have not yet been determined) to obtain critical area information for the layout design. The layout design can then be modified based upon the obtained critical area information. | 01-28-2010 |
| 20100162192 | Logic Injection - A technique for reducing a circuit listing. According to examples of the technique, at least a portion of a circuit listing is analyzed to identify occurrences of a circuit structure made up of a plurality of circuit components. For each identified occurrence of the defined circuit structure, an injection data object is created corresponding to the plurality of components, and the injection data object is substituted into the portion of the circuit listing in place of the plurality of components. For each occurrence of the defined structure, one or more properties of the occurrence of the defined structure may be determined and contained by the corresponding injection data object. | 06-24-2010 |
| 20100185994 | Topological Pattern Matching - Techniques for more efficiently identifying specific topological patterns in microdevice design data, such as layout design data. A user provides a topological pattern matching tool with a pattern template. In response, the topological pattern matching tool will analyze the pattern template to create a set of “design rule check” operations that can be performed to identify topological features of the layout design that will include the set of topological features specified for the template. The topological pattern matching tool also specifies properties that should be determined for each set of topological features identified by a design rule check operation. Once the design rule check operations have been created, the tool applies them to the layout design data being analyzed. The results produced by the design rule check operations will be a group of topological features in the layout design that encompass the topological features specified for the template. The results also will include a set of properties for each of the identified topological features. Next, the pattern matching tool creates a search graph based upon the results of the design rule check operations. Once the search graph is constructed, the pattern matching tool traverses the search graph to identify combinations of nodes connected by graph edges representing feature characteristics that match the constraints specified for the pattern template. For each such identified combination of nodes, the tool will output the arrangement of geometric elements corresponding to the nodes as a topological match to the original template. | 07-22-2010 |
| 20100185995 | Electrostatic Damage Protection Circuitry Verification - Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to (or beyond) the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified. If there are any remaining interconnect lines that have not been determined to exceed the specified maximum impedance component value through the use of the analysis window, then the impedance component values of these remaining interconnect lines can be specifically determined using a parasitic extraction process. | 07-22-2010 |
| 20100199107 | SECURE EXCHANGE OF INFORMATION IN ELECTRONIC DESIGN AUTOMATION - Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same. For instance, the tool may be a physical verification tool capable of verifying whether any of the one or more integrated circuit layouts may violate one or more of the secured rules. An error report may be generated without revealing the secured rules. | 08-05-2010 |
| 20100229133 | Property-Based Classification In Electronic Design Automation - One or more properties can be associated with a design object in a microdevice design. These properties then can be used to classify relationships in a circuit design, such as a layout circuit design. In some implementations, the various relationships can be classified based upon the similarity or dissimilarity of the associated property values. | 09-09-2010 |
| 20110145770 | Device Annotation - An electronic design automation process, such as a layout-verses-schematic analysis process, may recognize a representation of a device from physical layout design data. Information, such as geometric information separately obtained from the physical layout design data, is then associated with the recognized device representation. The associated information can subsequently be used in a later electronic design automation operation involving the recognized device representation. | 06-16-2011 |
| 20110145772 | Modular Platform For Integrated Circuit Design Analysis And Verification - A modular electronic design automation tool platform for analyzing and verifying an integrated circuit design. The platform may provide a single, unified database that can contain both logical information and physical information relating to an integrated circuit design, together with a plurality of electronic design automation operation execution modules for performing one or more desired electronic design automation operations. The platform may also provide export modules and import modules. An export module extracts relevant data from the database, and configures that data for use by a specific electronic design automation operation execution module. An import module then receives output data from a particular electronic design automation operation execution module, configures that data for integration into the unified database, and then imports the configured data into the database. | 06-16-2011 |
