| Patent application number | Description | Published |
|---|
| 20080233704 | Integrated Resistor Capacitor Structure - A resistor capacitor structure and a method of fabrication. A resistor capacitor structure provides a capacitance between at least two nodes within a microelectronic circuit. A bottom plate of the resistor capacitor structure comprises a resistance layer, which in turn provides a resistance path between an additional node within the circuit. The resistor capacitor structure may be formed on top or within interlevel dielectric layers. The resistance layer, alternatively, may be used to fill a cavity located between interlevel dielectric layers and accordingly provide a resistance path between the interlevel dielectric layers. | 09-25-2008 |
| 20080254590 | Fabrication process for silicon-on-insulator field effect transistors using high temperature nitrogen annealing - Disclosed is a method of fabricating a silicon-on-insulator (SOI) device that enables high device densities and mitigates variances in carrier mobility and saturation drain current (Id | 10-16-2008 |
| 20090065866 | Non-Planar Silicon-On-Insulator Device that Includes an "Area-Efficient" Body Tie - Non-planar SOI devices that include an “area-efficient” body tie are disclosed. The device includes a bulk substrate, an insulator layer formed on a surface of the bulk substrate, and a silicon body formed on a surface of the insulator layer. The silicon body preferably includes (i) a non-planar channel connecting a source region and a drain region, and (ii) a body tie that is adjacent to the channel and couples the channel to a voltage potential. The device further includes a gate dielectric formed on the channel and a gate material formed on the gate dielectric. | 03-12-2009 |
| 20100117153 | HIGH VOLTAGE SOI CMOS DEVICE AND METHOD OF MANUFACTURE - A high voltage FET and process for fabricating such an FET are provided. An extended drain and thick gate oxide device design is implemented in a basic CMOS structure to enable higher operating voltages. The basic concept of the invention is well suited for the body-tie architecture often utilized in this technology and is also applicable to other SOI processes using similar isolation schemes. | 05-13-2010 |
| 20100214009 | METHOD FOR DIGITAL PROGRAMMABLE OPTIMIZATION OF MIXED-SIGNAL CIRCUITS - A method for digital programmable optimization of a mixed-signal circuit is provided. The method comprises dividing up one or more transistor devices of the mixed-signal circuit into one or more transistor segments, with each transistor segment including a body tie bias terminal. Each body tie bias terminal is coupled to at least one voltage bias, either by placing each body tie bias terminal in signal communication with one or more bias nodes in the mixed-signal circuit, or by placing each body tie bias terminal in signal communication with a non-precision bias voltage source. Each body tie terminal is also arranged to be in signal communication with a separate one of one or more digital programmable storage elements. | 08-26-2010 |
| 20110089331 | Neutron Detector Cell Efficiency - Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production. | 04-21-2011 |
