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| 20090282532 | PLANTS AND SEEDS OF HYBRID CORN VARIETY CH030594 - According to the invention, there is provided seed and plants of the hybrid corn variety designated CH030594. The invention thus relates to the plants, seeds and tissue cultures of the variety CH030594, and to methods for producing a corn plant produced by crossing a corn plant of variety CH030594 with itself or with another corn plant, such as a plant of another variety. The invention further relates to genetic complements of plants of variety CH030594. | 11-12-2009 |
| 20090282575 | PLANTS AND SEEDS OF HYBRID CORN VARIETY CH600622 - According to the invention, there is provided seed and plants of the hybrid corn variety designated CH600622. The invention thus relates to the plants, seeds and tissue cultures of the variety CH600622, and to methods for producing a corn plant produced by crossing a corn plant of variety CH600622 with itself or with another corn plant, such as a plant of another variety. The invention further relates to genetic complements of plants of variety CH600622. | 11-12-2009 |
| 20090288197 | PLANTS AND SEEDS OF HYBRID CORN VARIETY CH862061 - According to the invention, there is provided seed and plants of the hybrid corn variety designated CH862061. The invention thus relates to the plants, seeds and tissue cultures of the variety CH862061, and to methods for producing a corn plant produced by crossing a corn plant of variety CH862061 with itself or with another corn plant, such as a plant of another variety. The invention further relates to genetic complements of plants of variety CH862061. | 11-19-2009 |
| 20090288198 | PLANTS AND SEEDS OF HYBRID CORN VARIETY CH288631 - According to the invention, there is provided seed and plants of the hybrid corn variety designated CH288631. The invention thus relates to the plants, seeds and tissue cultures of the variety CH288631, and to methods for producing a corn plant produced by crossing a corn plant of variety CH288631 with itself or with another corn plant, such as a plant of another variety. The invention further relates to genetic complements of plants of variety CH288631. | 11-19-2009 |
| 20100263081 | PLANTS AND SEEDS OF HYBRID CORN VARIETY CH127588 - According to the invention, there is provided seed and plants of the hybrid corn variety designated CH127588. The invention thus relates to the plants, seeds and tissue cultures of the variety CH127588, and to methods for producing a corn plant produced by crossing a corn plant of variety CH127588 with itself or with another corn plant, such as a plant of another variety. The invention further relates to genetic complements of plants of variety CH127588. | 10-14-2010 |
| 20100269195 | PLANTS AND SEEDS OF HYBRID CORN VARIETY CH482178 - According to the invention, there is provided seed and plants of the hybrid corn variety designated CH482178. The invention thus relates to the plants, seeds and tissue cultures of the variety CH482178, and to methods for producing a corn plant produced by crossing a corn plant of variety CH482178 with itself or with another corn plant, such as a plant of another variety. The invention further relates to genetic complements of plants of variety CH482178. | 10-21-2010 |
| 20110107452 | PLANTS AND SEEDS OF HYBRID CORN VARIETY CH958300 - According to the invention, there is provided seed and plants of the hybrid corn variety designated CH958300. The invention thus relates to the plants, seeds and tissue cultures of the variety CH958300, and to methods for producing a corn plant produced by crossing a corn plant of variety CH958300 with itself or with another corn plant, such as a plant of another variety. The invention further relates to genetic complements of plants of variety CH958300. | 05-05-2011 |
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| 20090190410 | USING DIFFERENTIAL DATA STROBES IN NON-DIFFERENTIAL MODE TO ENHANCE DATA CAPTURE WINDOW - A data capture circuit includes strobes that track input data even when conditions arise that cause the differences in skew from interpreting data state ones and zeros. This is accomplished whether these skews arise from reference voltage variation, data pattern loading, power supply droop, process variations within the chip itself, or other causes. The differential input strobes of the data capture circuit are input into individual input buffers, each compared against a reference voltage individually, as well as a data input pin. The outputs from these buffers are maintained separate from each other all the way to the point where the input data is latched. In latching the input data, data ones are latched entirely based on input signals derived from a rising edge (both strobes and data), and zeros are latched entirely based on input signals derived from a falling edge (both strobes and data). | 07-30-2009 |
| 20090300255 | SHIELDING OF DATALINES WITH PHYSICAL PLACEMENT BASED ON TIME STAGGERED ACCESS - A bus driver circuit divides an internal data bus for an integrated circuit memory into at least two groups, designated by speed. A faster group of data lines and a slower group of data lines are placed in an interleaved fashion in order to provide a two group shielding solution. At the earliest opportunity following the reception of a read command, the data from memory banks in the memory is sorted into these two groups. For a DDR3 memory, the sorting method is based on the A2 column address, known as C2. All of the data is brought out of the banks in parallel and sorted as it enters the main amplifiers. These main amplifiers are also divided into two groups, faster and slower. Each amplifier then connects to a data line (G-line) of the same group. The clock assigned to the fast group fires right away, thereby connecting the data associated with the fast amplifiers to the fast data group. This data group then proceeds to the output buffers through the entire data path as fast as possible. The second, slower data group is started with a delayed clock signal and proceeds through the data path to the output buffer maintaining a fixed delay. Since the first and second data groups are not switching at the same time they act as shields to one another. | 12-03-2009 |
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| 20080285371 | WIDE WINDOW CLOCK SCHEME FOR LOADING OUTPUT FIFO REGISTERS - A circuit provides the widest possible window for capturing data and preventing run-through in a FIFO register. The FIFO register includes two registers per I/O. Two FIFO input clocks are used, one for each FIFO register. When one FIFO clock is active, the other is automatically disabled. Initially, the circuit is reset such that one clock is active, and the other disabled. Upon receiving a valid READ command, a shift chain attached to the FICLK that is currently low begins counting the clock cycles. This eventually determines when the FICLK that is currently low can be enabled. The final enable is dependent upon the turning off the FICLK that is currently high. The FICLK that is enabled during the reset turns off a fixed delay after the falling edge of the YCLK associated with the READ command. | 11-20-2008 |
| 20080291748 | WIDE WINDOW CLOCK SCHEME FOR LOADING OUTPUT FIFO REGISTERS - A circuit provides the widest possible window for capturing data and preventing run-through in a FIFO register. The FIFO register includes two registers per I/O. Two FIFO input clocks are used, one for each FIFO register. When one FIFO clock is active, the other is automatically disabled. Initially, the circuit is reset such that one clock is active, and the other disabled. Upon receiving a valid READ command, a shift chain attached to the FICLK that is currently low begins counting the clock cycles. This eventually determines when the FICLK that is currently low can be enabled. The final enable is dependent upon the turning off the FICLK that is currently high. The FICLK that is enabled during the reset turns off a fixed delay after the falling edge of the YCLK associated with the READ command. | 11-27-2008 |
| 20090231944 | MULTI-BANK BLOCK ARCHITECTURE FOR INTEGRATED CIRCUIT MEMORY DEVICES HAVING NON-SHARED SENSE AMPLIFIER BANDS BETWEEN BANKS - A multi-bank block architecture for integrated circuit memory devices which effectively reduces the total length of the datapath for a given input/output (I/O) from the memory cells in the memory array to the actual device I/O pad. In accordance with the present, a memory block in a memory device is effectively divided into two or more banks, and between these banks an additional non-shared sense amplifier band is added as a sense amplifier cannot be shared across a bank boundary. Within this multi-bank block, separate data paths are provided for the banks with the column (Y-Select) lines being common. | 09-17-2009 |
| 20090231945 | ASSYMETRIC DATA PATH POSITION AND DELAYS TECHNIQUE ENABLING HIGH SPEED ACCESS IN INTEGRATED CIRCUIT MEMORY DEVICES - An asymmetric data path position and delays technique enabling high speed access in integrated circuit memory devices which is asymmetric in terms of the delay from the array to the I/O buffers based on the position relative within a known starting address of a pre-fetch field. In accordance with the technique of the present invention, the delay is not only asymmetric in terms of its physical length, but also in the number of pipeline stages and the clocks that control them and can also be asymmetric in terms of the column address required to access each section of the array and its designated pre-fetch field. | 09-17-2009 |
