| Patent application number | Description | Published |
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| 20090031091 | CONTINUOUS TIMING CALIBRATED MEMORY INTERFACE - A system that adjusts the timing of write operations at a memory controller is described. This system operates by observing timing drift for read data at the memory controller, and then adjusting the timing of write operations at the memory controller based on the observed timing drift for the read data. | 01-29-2009 |
| 20100025811 | INTEGRATED CIRCUIT WITH BUILT-IN HEATING CIRCUITRY TO REVERSE OPERATIONAL DEGENERATION - An integrated circuit device ( | 02-04-2010 |
| 20100046600 | Methods and Circuits for Asymmetric Distribution of Channel Equalization Between Devices - A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC. | 02-25-2010 |
| 20100235554 | RECONFIGURABLE POINT-TO-POINT MEMORY INTERFACE - Embodiments of an apparatus are described. An interface circuit in this apparatus receives or transmits digital signals on a bus and is configured to alternatively operate as either a data-bus interface circuit or a control-bus interface circuit in dependence upon a mode setting stored in a register. For example, the interface circuit may be pre-configured to interpret a line of an external bus as either a data line or a control line in accordance with the stored mode setting. Moreover, the stored mode setting may be dynamically configured (e.g., reprogrammed) during operation of the interface circuit so that subsequent digital signals are subsequently handled in accordance with a new mode setting. | 09-16-2010 |
| 20100239057 | DRIFT CANCELLATION TECHNIQUE FOR USE IN CLOCK-FORWARDING ARCHITECTURES - A circuit includes a frequency synthesizer, N phase mixers coupled to the frequency synthesizer, a plurality of receivers, and a calibration circuit. The frequency synthesizer is to receive a reference clock signal and is to output a primary clock signal. A respective phase mixer in the N phase mixers is to output a respective secondary clock signal having a corresponding phase. A respective receiver in the plurality of receivers is coupled to two of the N phase mixers, and at a respective time is to receive data in accordance with the respective secondary clock signal from one of the two phase mixers coupled to the respective receiver. The calibration circuit is to calibrate a secondary clock signal output by a respective phase mixer in the N phase mixers by adjusting the phase of the secondary clock signal of the respective phase mixer. | 09-23-2010 |
| 20100281289 | Bidirectional Memory Interface with Glitch Tolerant Bit Slice Circuits - A bit slice circuit having transmit and receive modes of operation is described. The bit slice circuit comprises: first transmit circuitry and first receive circuitry operating in a first clock domain, wherein the first circuitry receives a first clock signal; second transmit circuitry and second receive circuitry operating in a second clock domain, wherein the second circuitry receives a second clock signal; transmit transition circuitry and receive transition circuitry, the transmit transition circuitry coupling the first transmit circuitry to the second transmit circuitry, the receive transition circuitry coupling the first receive circuitry to the second receive circuitry, wherein the transition circuitry receives the first and second clock signals; and a single phase mixer that generates the second clock signal, wherein the second clock signal has a first phase in the transmit mode of operation and second phase in the receive mode of operation. | 11-04-2010 |
| 20110222594 | Methods and Circuits for Asymmetric Distribution of Channel Equalization Between Devices - A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC. | 09-15-2011 |
| Patent application number | Description | Published |
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| 20090276558 | LANE MERGING - A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data words from each of the active data lanes are merged onto the parallel bus in a pre-defined repeating sequence of data lanes. This approach allows other, non-active, data lanes to remain in a power conservation state. | 11-05-2009 |
| 20090315899 | GRAPHICS MULTI-MEDIA IC AND METHOD OF ITS OPERATION - A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a protocol defined for a display serial interface, and a uni-directional serial link which accords to a compatible protocol defined for a camera serial interface. The GMIC receives packets according to the protocol from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets according to the protocol to the host over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a memory operation at the memory of the host. The GMIC may be connected to a display over a bi-directional serial link according to the display serial interface protocol and to a camera over a uni-directional serial link and a bi-directional control link according to the camera serial interface so that the host controls the display and camera indirectly through the GMIC. | 12-24-2009 |
| 20100185800 | COMMUNICATION PROTOCOL FOR SHARING MEMORY RESOURCES BETWEEN COMPONENTS OF A DEVICE - In a device, such as a cell phone, memory resource sharing is enabled between components, such as integrated circuits, each of which has memory resources. This may be accomplished by providing an interconnect between the components and constructing transaction units which are sent over the interconnect to initiate memory access operations. The approach may also be used to allow for a degree of communication between device components. | 07-22-2010 |
| Patent application number | Description | Published |
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| 20080209654 | Anti-Smear Cleaning Swab with Perforated Blade - An anti-smear cleaning swab for cleaning delicate surfaces, comprising a body defining an elongated shaft having two opposite ends. An enlarged blade is carried at one end of the handle. A number of bores are made through the blade, these bores enabling both fluid flow therethrough and also some retensive capture of fluid droplets. A fluid absorbing cloth sheet pocket generally encloses by folding same around the blade, and is sized to fit snugly therearound. | 09-04-2008 |
| 20100186771 | PORTABLE DUSTING TOOL - There is provided a non-scrubbing dusting tool for cleaning the exposed surface of a digital camera sensor lens in a recessed digital camera sensor chamber. The dusting tool comprises a dust brush having an elongated shank with a tuft of bristles having electrostatic charge built up therein at one end, and a handle at the other end. The tuft of bristles is V-shape and its free end tips are bevelled, for best performance. The duster is sized to adjustably fit inside the digital camera sensor chamber in such a fashion that the bristles leading edge tips will be able to reach all of the exposed surface of the camera sensor lens while avoiding contaminating contact with the camera sensor chamber. In an operative sensor lens cleaning condition of the dusting tool, the dust brush remains motionless relative to the handle while the dusting tool bristles leading edge tips are manually swept over the camera sensor lens to be cleaned. When the dusting tool is not in use, a rotating motor may spin the dust brush so that the bristles fan out under centrifugal force, so as to remove dust collected by the bristles during cleaning operations. | 07-29-2010 |
| 20100188841 | LOUPE AND LIGHTING ASSEMBLY FOR CAMERA SENSOR DUST DETECTION - A loupe and lighting assembly for enhancing detection of dust particles on the optical sensor of a digital camera. The assembly is made of a cylindroid hollow-centered main frame body, into which is fixed a loupe lens. A battery housing is joined to the body in order to supply electrical power to a LED array. The LED array is made from a plurality of LED diodes mounted peripherally and around the inside of the cylindroid body, being tilted at an acute angle from the axis orthogonal to the plane of the cylindroid body so that all diodes axially converge toward a single focal point, at a certain distance from the main frame body. The dust particles scattered upon the sensor become clearly visible to an observer looking through the assembly when the dust particles location coincide with the LED common focal point. | 07-29-2010 |
| 20110197930 | SPRAY BULB CLEANER FOR DIGITAL CAMERA SENSORS - A spray bulb cleaner is provided for removing dust from digital camera sensors. The cleaner comprises a compressible yet resilient manually actuatable bulb body defining a deformable wall circumscribing an air enclosure. The bulb wall has an air outlet enabling air outflow from the bulb air enclosure toward ambient air when the bulb is squeezed and becomes deformed. The bulb wall also has an air intake enabling ambient air inflow into the bulb air enclosure. A releasable first one-way valve mounted at the air intake, controls air inflow from ambient air towards the bulb enclosure. A releasable second one-way valve mounted at a tubular nozzle inner end portion controls air outflow from the bulb air enclosure toward ambient air. The nozzle is mounted at to the bulb air outlet. At least a portion of the spray bulb is made from an electrostatically charged ionizing compound for neutralizing a target surface to be dusted by the spray bulb cleaner. A filter member can be mounted adjacent either the first or second one-way valves. | 08-18-2011 |
