Patent application number | Description | Published |
20080250233 | Providing thread fairness in a hyper-threaded microprocessor - A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline. | 10-09-2008 |
20090187712 | Operation Frame Filtering, Building, And Execution - The present subject matter relates to operation frame filtering, building, and execution. Some embodiments include identifying a frame signature, counting a number of execution occurrences of the frame signature, and building a frame of operations to execute instead of operations identified by the frame signature. | 07-23-2009 |
20110055524 | PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR - A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline. | 03-03-2011 |
20110055525 | PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR - A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline. | 03-03-2011 |
20110153994 | Multiplication Instruction for Which Execution Completes Without Writing a Carry Flag - A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium. | 06-23-2011 |
20140052963 | TECHNIQUE TO PERFORM THREE-SOURCE OPERATIONS - A technique to perform three-source instructions. At least one embodiment of the invention relates to converting a three-source instruction into at least two instructions identifying no more than two source values. | 02-20-2014 |
20150186299 | LOAD INSTRUCTION FOR CODE CONVERSION - Embodiments of an invention for a load instruction for code conversion are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction having a source operand to indicate a source location and a destination operand to indicate a destination location. The execution unit is to execute the instruction. Execution of the instruction includes checking the access permissions of the source location and loading content from the source location into the destination location if the access permissions of the source location indicate that the content is executable. | 07-02-2015 |
Patent application number | Description | Published |
20110153993 | Add Instructions to Add Three Source Operands - A method in one aspect may include receiving an add instruction. The add instruction may indicate a first source operand, a second source operand, and a third source operand. A sum of the first, second, and third source operands may be stored as a result of the add instruction. The sum may be stored partly in a destination operand indicated by the add instruction and partly a plurality of flags. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium. | 06-23-2011 |
20110161635 | Rotate instructions that complete execution without reading carry flag - A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag. | 06-30-2011 |
20130227252 | Add Instructions to Add Three Source Operands - A method in one aspect may include receiving an add instruction. The add instruction may indicate a first source operand, a second source operand, and a third source operand. A sum of the first, second, and third source operands may be stored as a result of the add instruction. The sum may be stored partly in a destination operand indicated by the add instruction and partly a plurality of flags. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium. | 08-29-2013 |
20130275733 | MULTI-LEVEL TRACKING OF IN-USE STATE OF CACHE LINES - This disclosure includes tracking of in-use states of cache lines to improve throughput of pipelines and thus increase performance of processors. Access data for a number of sets of instructions stored in an instruction cache may be tracked using an in-use array in a first array until the data for one or more of those sets reach a threshold condition. A second array may then be used as the in-use array to track the sets of instructions after a micro-operation is inserted into the pipeline. When the micro-operation retires from the pipeline, the first array may be cleared. The process may repeat after the second array reaches the threshold condition. During the tracking, an in-use state for an instruction line may be detected by inspecting a corresponding bit in each of the arrays. Additional arrays may also be used to track the in-use state. | 10-17-2013 |
20140059333 | METHOD, APPARATUS, AND SYSTEM FOR SPECULATIVE ABORT CONTROL MECHANISMS - An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions. | 02-27-2014 |
20140189306 | ENHANCED LOOP STREAMING DETECTOR TO DRIVE LOGIC OPTIMIZATION - An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled. | 07-03-2014 |
20140195790 | PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION - A secondary jump execution unit (JEU) is incorporated in a micro-processor to operate concurrently with a primary JEU, enabling the execution of simultaneous branch operations with possible detection of multiple branch mispredicts. When branch operations are executed on both JEUs in a same instruction cycle, mispredict processing for the secondary JEU is skidded into the primary JEU's dispatch pipeline such that the branch processing for the secondary JEU occurs after processing of the branch for the primary JEU and while the primary JEU is not processing a branch. Moreover, in cases when a nuke command is also received from a reorder buffer of the processor, the branch processing for the secondary JEU is further delayed to accommodate processing of the nuke on the primary JEU. Further embodiments support the promotion of the secondary JEU to have access to the mispredict mechanisms of the primary JEU in certain circumstances. | 07-10-2014 |
20150032998 | METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL INSTRUCTIONS - An apparatus and method is described herein for providing speculation control instructions. An xAcquire and xRelease instruction are provided to define a critical section. In one embodiment, the xAcquire instruction includes a lock instruction with an elision prefix and the xRelease instruction includes a lock release instruction with an elision prefix. As a result, a processor is able to elide locks and transactionally execute a critical section defined in software by xAcquire and xRelease. But by adding only prefix hints, legacy processor are able to execute the same code by just ignoring the hints and executing the critical section traditionally with locks to guarantee mutual exclusion. Moreover, xBegin and xEnd are similarly provided for in an Instruction Set Architecture (ISA) to define a transactional code region. In addition, other control speculation instructions, such as xAbort to enable explicit abort of a critical or transactional code section and xTest to test a state of speculative execution is also provided in the ISA. | 01-29-2015 |
20150089199 | ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION EITHER WITHOUT WRITING OR READING FLAGS - A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag. | 03-26-2015 |
20150089200 | ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION EITHER WITHOUT WRITING OR READING FLAGS - A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag. | 03-26-2015 |
20150089201 | ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION EITHER WITHOUT WRITING OR READING FLAGS - A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag. | 03-26-2015 |
Patent application number | Description | Published |
20110080686 | MIM CAPACITOR - A method of forming a metal-insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface. | 04-07-2011 |
20110086468 | ASSEMBLY OF SEMICONDUCTOR CHIPS/WAFERS - A method for assembling a first semiconductor chip provided with pads on a second semiconductor chip or wafer provided with pads, comprising covering the chip(s) with a dielectric, superposing the two chips, the pads being arranged substantially opposite to each other, and applying a voltage difference between the pads of the first and second chips to cause a breakdown of the dielectric and a diffusion of the conductor forming the pads into the broken down areas, whereby a conductive path forms between the opposite pads. | 04-14-2011 |
20110095437 | INTERFACE PLATE BETWEEN INTEGRATED CIRCUITS - An interface plate capable of being mounted between first and second surface-mounted electronic chips. The plate includes a plurality of first, second, and third through openings, the first openings being filled with a conductive material and being arranged to be in front of pads of the first and second chips during the assembly, the second openings being filled with a second material, the third openings being filled with a third material, the second and third materials forming two complementary components of a thermoelectric couple. | 04-28-2011 |
20110140231 | INTEGRATED MICROELECTRONIC DEVICE WITH THROUGH-VIAS - An integrated microelectronic device is formed from a substrate having a first side and a second side and including a doped active zone ( | 06-16-2011 |
20120074527 | INTEGRATED CIRCUIT COMPRISING A DEVICE WITH A VERTICAL MOBILE ELEMENT INTEGRATED IN A SUPPORT SUBSTRATE AND METHOD FOR PRODUCING THE DEVICE WITH A MOBILE ELEMENT - The integrated circuit comprises a support substrate having opposite first and second main surfaces. A cavity passes through the support substrate and connects the first and second main surfaces. The integrated circuit comprises a device with a mobile element, the mobile element and a pair of associated electrodes of which are included in a cavity. An anchoring node of the mobile element is located at the level of the first main surface. The integrated circuit comprises a first elementary chip arranged at the level of the first main surface and electrically connected to the device with a mobile element. | 03-29-2012 |
20120133020 | SEMICONDUCTOR DEVICE COMPRISING A CAPACITOR AND AN ELECTRICAL CONNECTION VIA AND FABRICATION METHOD - A dielectric wafer has, on top of its front face, a front electrical connection including an electrical connection portion. A blind hole passes through from a rear face of the wafer to at least partially reveal a rear face of the electrical connection portion. A through capacitor is formed in the blind hole. The capacitor includes a first conductive layer covering the lateral wall and the electrical connection portion (forming an outer electrode), a dielectric intermediate layer covering the first conductive layer (forming a dielectric membrane), and a second conductive layer covering the dielectric intermediate layer (forming an inner electrode). A rear electrical connection is made to the inner electrode. | 05-31-2012 |
20130286540 | MIM CAPACITOR - A method of forming a metal- insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface. | 10-31-2013 |