| Patent application number | Description | Published |
|---|
| 20080250233 | Providing thread fairness in a hyper-threaded microprocessor - A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline. | 10-09-2008 |
| 20090187712 | Operation Frame Filtering, Building, And Execution - The present subject matter relates to operation frame filtering, building, and execution. Some embodiments include identifying a frame signature, counting a number of execution occurrences of the frame signature, and building a frame of operations to execute instead of operations identified by the frame signature. | 07-23-2009 |
| 20110055524 | PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR - A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline. | 03-03-2011 |
| 20110055525 | PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR - A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline. | 03-03-2011 |
| 20110153994 | Multiplication Instruction for Which Execution Completes Without Writing a Carry Flag - A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium. | 06-23-2011 |
| Patent application number | Description | Published |
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| 20110080686 | MIM CAPACITOR - A method of forming a metal-insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface. | 04-07-2011 |
| 20110086468 | ASSEMBLY OF SEMICONDUCTOR CHIPS/WAFERS - A method for assembling a first semiconductor chip provided with pads on a second semiconductor chip or wafer provided with pads, comprising covering the chip(s) with a dielectric, superposing the two chips, the pads being arranged substantially opposite to each other, and applying a voltage difference between the pads of the first and second chips to cause a breakdown of the dielectric and a diffusion of the conductor forming the pads into the broken down areas, whereby a conductive path forms between the opposite pads. | 04-14-2011 |
| 20110095437 | INTERFACE PLATE BETWEEN INTEGRATED CIRCUITS - An interface plate capable of being mounted between first and second surface-mounted electronic chips. The plate includes a plurality of first, second, and third through openings, the first openings being filled with a conductive material and being arranged to be in front of pads of the first and second chips during the assembly, the second openings being filled with a second material, the third openings being filled with a third material, the second and third materials forming two complementary components of a thermoelectric couple. | 04-28-2011 |
| 20110140231 | INTEGRATED MICROELECTRONIC DEVICE WITH THROUGH-VIAS - An integrated microelectronic device is formed from a substrate having a first side and a second side and including a doped active zone ( | 06-16-2011 |
| 20120074527 | INTEGRATED CIRCUIT COMPRISING A DEVICE WITH A VERTICAL MOBILE ELEMENT INTEGRATED IN A SUPPORT SUBSTRATE AND METHOD FOR PRODUCING THE DEVICE WITH A MOBILE ELEMENT - The integrated circuit comprises a support substrate having opposite first and second main surfaces. A cavity passes through the support substrate and connects the first and second main surfaces. The integrated circuit comprises a device with a mobile element, the mobile element and a pair of associated electrodes of which are included in a cavity. An anchoring node of the mobile element is located at the level of the first main surface. The integrated circuit comprises a first elementary chip arranged at the level of the first main surface and electrically connected to the device with a mobile element. | 03-29-2012 |
| 20120133020 | SEMICONDUCTOR DEVICE COMPRISING A CAPACITOR AND AN ELECTRICAL CONNECTION VIA AND FABRICATION METHOD - A dielectric wafer has, on top of its front face, a front electrical connection including an electrical connection portion. A blind hole passes through from a rear face of the wafer to at least partially reveal a rear face of the electrical connection portion. A through capacitor is formed in the blind hole. The capacitor includes a first conductive layer covering the lateral wall and the electrical connection portion (forming an outer electrode), a dielectric intermediate layer covering the first conductive layer (forming a dielectric membrane), and a second conductive layer covering the dielectric intermediate layer (forming an inner electrode). A rear electrical connection is made to the inner electrode. | 05-31-2012 |
