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Fang, Hsinchu
Ce-Min Fang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110044388 | SYSTEMS AND METHODS OF FLEXIBLE POWER MANAGEMENT APPLICABLE TO DIGITAL BROADCASTING - A system for receiving a digital broadcast includes an input terminal that receives the digital broadcast containing scalable data, and a controller for controlling an operation mode of the system. In addition, the system may also include a processor that decodes the data, and a power management device that varies the amount of data to be decoded according to the operation mode. | 02-24-2011 |
Huang-Sheng Fang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110102362 | Writing and displaying device - A writing and displaying device is proposed, including: a display member having a first electric connecting portion and an electrochromic layer; an input member including a second electric connecting portion and an electrolyte layer; and a power supply member for supplying electric power to the input member and the display member. When the electric power is supplied by the power supply member and the input member is in contact with the display member, the input member, the display member and the power supply member constitute a loop circuit such that an electrochromism occurs to the portion of the display member in contact with the input member. The electrochromism can be maintained for a predetermined duration of time even after the contact of the display member with the input member is removed and the driving power is turned off. | 05-05-2011 |
Hui-Chia Fang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080198516 | Electrostatic discharge (ESD) protection device and method therefor - A method and device for providing electrostatic discharge (ESD) protection are disclosed. The method uses the gate-controlled conductivity of field n-channel metal-oxide-semiconductor field effect transistor (field NMOSFET), wherein considerable ESD current can be conducted away when any ESD event beyond range of operation voltage, unlike PMOS ESD protection which is to be turned on at negative voltage. Instead of the traditional two-stage ESD protection (using one ESD protection between open drain output and V | 08-21-2008 |
Jen-Yu Fang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080239728 | LIGHT CONTROL DEVICE HAVING MODIFIED PRISM STRUCTURE - The light control device provides fillings in the valleys of the prism elements, be it uniformly or non-uniformly arranged, which is made of UV and/or thermal curable resins of an appropriate refractive index different from that of the prism elements. The optical performance of the original prism elements can be altered by the following approaches. First, the refractive index of the fillings can be appropriately chosen. Second, the fillings can be up to an appropriate height (but never overruns the surrounding prism elements). Third, the distribution of the height or the refractive index of the fillings across the light emission plane can be “patterned,” that is, in accordance with the planar light intensity distribution produced by the light source. | 10-02-2008 |
Li-Chih Fang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080272489 | Package substrate and its solder pad - A semiconductor chip substrate with solder pad includes: a core layer and at least one conductive structure formed on the surface of the core layer; an insulation layer with at least one patterned opening covering the conductive structure, wherein the patterned opening has a center portion and a plurality of wing portions on the peripheral edge of the center portion to define the exposed area of the conductive structure as the solder pad. The solder pad with wing will improve the adhesion effect between the solder pad and the solder ball. | 11-06-2008 |
| 20090137069 | Chip packaging process including simpification and mergence of burn-in test and high temperature test - A chip packaging process integrates a burn-in test or a high temperature test to simplify overall packaging and testing process flow. One or more chips are disposed on one or more units of a substrate strip where the substrate strip has a plurality of electrical open sections at the plating lines to electrically isolate the external pads between different units. After electrical connection and encapsulation, a burn-in test is executed at the same time of a post mold curing step, with a high-temperature testing if necessary. Therefore, the chips on the substrate strip has been gone through the burn-in test during the encapsulant is completely cured at the post mold curing step and the burn-in test is finished before the singulation step to reduce the overall testing time. | 05-28-2009 |
| 20090200685 | Electronic packaging method and apparatus - The present invention utilizes a panel substrate as the packaging substrate carried by a working susceptor. Packaging devices are hung in the nearby of the working susceptor and moved by robot arms to the working susceptor, whereby the problems of substrate warpage and substrate transportation are overcome. Further, identical or different packaging steps can be simultaneously performed in different areas of a panel substrate, whereby the cost is reduced and the product yield is promoted. | 08-13-2009 |
| 20100000384 | Method for cutting large-size wafer and apparatus for the same - The present invention discloses a method for cutting a large-size wafer and an apparatus for the same. The method of the present invention decreases the frequency of wafer transmission to reduce wafer damages, wherein a wafer is always carried by an identical working susceptor, and the working susceptor is moved to the related devices performing corresponding works, or wherein a wafer is always carried by an identical working susceptor, and the related devices are moved to the working susceptor to perform corresponding works. | 01-07-2010 |
Shih-Hao Fang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110138248 | METHOD FOR ARRANGING MEMORIES OF LOW-COMPLEXITY LDPC DECODER AND LOW-COMPLEXITY LDPC DECODER USING THE SAME - A method for arranging memories of a low-complexity low-density parity-check (LDPC) decoder and a low-complexity LDPC decoder using the same method are provided. The main idea of the method for arranging memories of a low-complexity LDPC decoder is to merge at least one or two small-capacity memory blocks into one memory group, so that the memory area can be reduced and the power consumption in reading or writing data is lowered. Besides, as the merged memory group shares the same address line in reading or writing data, at least one delay unit is used to adjust the reading or writing order and thereby ensure data validity. A low-complexity LDPC decoder using the disclosed method can meet the demands of high processing rate and low power consumption. | 06-09-2011 |
Shun-Lung Fang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110280798 | Cell Penetrating Peptides for Intracellular Delivery - The present invention provides a cell penetrating peptide which has following sequence: NYBX | 11-17-2011 |
Tuane Ying Fang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110226970 | SYSTEM AND METHOD FOR GENERATING DIRECT-WRITE PATTERN - A direct-write system is provided which includes a stage for holding a substrate, a processing module for processing pattern data and generating instructions associated with the pattern data, and an exposure module that includes beams that are focused onto the substrate and a beam controller that controls the beams in accordance with the instructions. The processing module includes vertex pair processors each having bit inverters. Each vertex pair processor is operable to process a respective vertex pair of an input scan line to generate an output scan line. Each bit inverter is operable to invert a respective input bit of the input scan line to generate a respective output bit of the output scan line if a bit position is located between the respective vertex pair, otherwise the respective input bit is copied to the respective output bit. The instructions correspond to the output bits for each beam. | 09-22-2011 |
Yu-Chao Fang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20120069529 | POWER CONVERSION MODULE - A power conversion module includes a circuit carrier board, a semiconductor module and an inductor module. The circuit carrier board has plural bonding pads. The semiconductor module is disposed on a first surface of the circuit carrier board. The inductor module has plural pins. The pins are extended from the inductor module along a first direction and connected with corresponding bonding pads on the circuit carrier board, so that a receptacle is defined between the inductor module and the circuit carrier board for accommodating the semiconductor module. | 03-22-2012 |
Yu Lung Fang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090256774 | Outdoor antenna box - The present invention provides an outdoor antenna box comprising a thermally conductive baseboard; a thermally conductive reflector in planar contact with the thermally conductive baseboard and has a first side face and a second side face; an antenna board securely mounted on the first side face of the thermally conductive reflector; a circuit board having a thermal body where the heat energy generated by the thermal body is transferred to the second side face of the thermally conductive reflector via a thermally conductive element; and a casing having an opening covered by the thermally conductive baseboard and an accommodation space that houses the thermally conductive reflector, the antenna board and the circuit board. | 10-15-2009 |
Ziwei Fang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20120100681 | METHOD OF MANUFACTURING SOURCE/DRAIN STRUCTURES - An integrated circuit device and method for manufacturing the integrated circuit device provide improved control over a shape of a trench for forming the source and drain features of integrated circuit device, by forming a second doped region in a first doped region and removing the first and the second doped regions by a first and a second wet etching processes. | 04-26-2012 |