| Patent application number | Description | Published |
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| 20080272814 | PARALLEL MULTIPLEXING DUTY CYCLE ADJUSTMENT CIRCUIT WITH PROGRAMMABLE RANGE CONTROL - A receive interface circuit includes a duty cycle adjustment circuit that adjusts the duty cycle of a reference clock signal based, at least in part, on a selected number of duty cycle adjustment units and a selected range of duty cycle adjustment. The duty cycle adjustment circuit may select as the reference clock signal one of a clock signal and at least a lower version of the clock signal in parallel with the duty cycle adjustment. | 11-06-2008 |
| 20080273528 | PHASE SELECT CIRCUIT WITH REDUCED HYSTERESIS EFFECT - A phase signal select circuit includes a supporting path coupled to a tri-state inverter circuit. The supporting path reduces effects of hysteresis on signal transfer. An apparatus includes at least one input node responsive to a respective one of at least one input signal. The apparatus includes at least one circuit coupled to a respective one of the at least one input node and coupled to an output node. Individual ones of the at least one circuit are configured to provide a version of the respective input signal to the output node in response to a first state of a respective select signal. The apparatus includes at least one second circuit coupled to a respective one of the at least one circuit. The at least one second circuit is configured to toggle nodes of the at least one circuit in response to a second state of the respective select signal. | 11-06-2008 |
| 20080297216 | TEST TECHNIQUES FOR A DELAY-LOCKED LOOP RECEIVER INTERFACE - An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal. | 12-04-2008 |
| 20100171547 | PSEUDO BANDGAP VOLTAGE REFERENCE CIRCUIT - A pseudo bandgap voltage reference circuit includes a first transistor and a second transistor, each coupled to a supply voltage node. The circuit also includes an amplifier circuit coupled to a gate terminal of each of the first and the second transistors, a current source coupled to the supply voltage node, and a first diode coupled between the current source and a ground reference node. A first input of the amplifier circuit is coupled to a node between the current source and the first diode. In addition, a first terminal of the first transistor is coupled to a second input of the amplifier circuit in a feedback loop. Also, an output reference voltage is developed at an output node coupled to a second terminal of the second transistor. Further, an output current of the current source is independent of a current flowing through the first terminal of the first transistor. | 07-08-2010 |
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| 20090150836 | Intelligent Pattern Signature Based on Lithography Effects - The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern signature can represent a group of design patterns that are equivalents from a lithography perspective. | 06-11-2009 |
| 20090169114 | INTERPOLATION OF IRREGULAR DATA IN A FINITE-DIMENSIONAL METRIC SPACE IN LITHOGRAPHIC SIMULATION - A method, system, and computer program product for preprocessing a pattern in a library of patterns and querying a preprocessed library of patterns are disclosed. Embodiments for querying a preprocessed library of patterns are disclosed for determining a distance between the representation for the first pattern and the representation for the second pattern, determining whether the distance between the representation for the first pattern and the representation for the second pattern is within the range for the first pattern, and transforming the second pattern with the transformation matrix to provide information about the second pattern. Embodiments for preprocessing a pattern in a library of patterns are disclosed for determining a transformation matrix for the first pattern, determining a range for the first pattern, wherein a distance between a representation for a first pattern and a representation for a second pattern is within the range and the second pattern can be transformed with the transformation matrix to provide information about the second pattern, and associating the range and the transformation matrix with the first pattern. | 07-02-2009 |
| 20090199137 | SYSTEM AND METHOD FOR MULTI-EXPOSURE PATTERN DECOMPOSITION - Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern. | 08-06-2009 |
| 20090288047 | METHOD AND APPARATUS FOR USING A DATABASE TO QUICKLY IDENTIFY AND CORRECT A MANUFACTURING PROBLEM AREA IN A LAYOUT - One embodiment provides a system for using a database to quickly identify a manufacturing problem area in a layout. During operation, the system receives a first check-figure which identifies a first area in a first layout, wherein the first area is associated with a first feature. Next, the system determines a first sample using the first check-figure, wherein the first sample represents the first layout's geometry within a first ambit of the first check-figure, wherein the first sample's geometry is expected to affect the shape of the first feature. The system then performs a model-based simulation using the first sample to obtain a first simulation-result which indicates whether the first feature is expected to have manufacturing problems. Next, the system stores the first simulation-result in a database which is used to quickly determine whether a second feature is expected to have manufacturing problems. | 11-19-2009 |
| 20090307642 | METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT - A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers. | 12-10-2009 |
| 20110167397 | SYSTEM AND METHOD FOR MULTI-EXPOSURE PATTERN DECOMPOSITION - Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern. | 07-07-2011 |
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| 20080236618 | Cleaning of bonded silicon electrodes - Methods of cleaning plasma processing chamber components include contacting surfaces of the components with a cleaning solution, while avoiding damage of other surfaces or areas of the components by the cleaning solution. An exemplary plasma processing chamber component to be cleaning is an elastomer bonded electrode assembly having a silicon member with a plasma-exposed silicon surface, a backing member, and an elastomer bonding material between the silicon surface and the backing member. | 10-02-2008 |
| 20090321018 | PERIPHERALLY ENGAGING ELECTRODE CARRIERS AND ASSEMBLIES INCORPORATING THE SAME - In accordance with one embodiment of the present disclosure, an assembly is provided comprising a multi-component electrode and a peripherally engaging electrode carrier. The peripherally engaging electrode carrier comprises a carrier frame and a plurality of reciprocating electrode supports. The multi-component electrode is positioned in the electrode accommodating aperture of the carrier frame. The backing plate of the electrode comprises a plurality of mounting recesses formed about its periphery. The reciprocating electrode supports can be reciprocated into and out of the mounting recesses. Additional embodiments of broader and narrower scope are contemplated. | 12-31-2009 |
| 20090322199 | BACKSIDE MOUNTED ELECTRODE CARRIERS AND ASSEMBLIES INCORPORATING THE SAME - A carrier assembly is provided comprising a backside mounted electrode carrier and electrode mounting hardware. The backside mounted electrode carrier comprises an electrode accommodating aperture, which in turn comprises a sidewall structure that is configured to limit lateral movement of an electrode positioned in the aperture. The electrode accommodating aperture further comprises one or more sidewall projections that support the weight of an electrode positioned in the aperture. The electrode mounting hardware is configured to engage an electrode positioned in the electrode accommodating aperture from the backside of the carrier and urge the electrode against the sidewall projections so as to limit axial movement of the electrode in the electrode accommodating aperture. Additional embodiments of broader and narrower scope are contemplated. | 12-31-2009 |
| 20090325320 | PROCESSES FOR RECONDITIONING MULTI-COMPONENT ELECTRODES - A process for reconditioning a multi-component electrode comprising a silicon electrode bonded to an electrically conductive backing plate is provided. The process comprises: (i) removing metal ions from the multi-component electrode by soaking the multi-component electrode in a substantially alcohol-free DSP solution comprising sulfuric acid, hydrogen peroxide, and water and rinsing the multi-component electrode with de-ionized water; (ii) polishing one or more surfaces of the multi-component electrode following removal of metal ions there from; and (iii) removing contaminants from silicon surfaces of the multi-component electrode by treating the polished multi-component electrode with a mixed acid solution comprising hydrofluoric acid, nitric acid, acetic acid, and water and by rinsing the treated multi-component electrode with de-ionized water. Additional embodiments of broader and narrower scope are contemplated. | 12-31-2009 |
| 20100090711 | SYSTEM AND METHOD FOR TESTING AN ELECTROSTATIC CHUCK - The present invention provides a reliable, non-invasive, electrical test method for predicting satisfactory performance of electrostatic chucks (ESCs). In accordance with an aspect of the present invention, a parameter, e.g., impedance, of an ESC is measured over a frequency band to generate a parameter functions. This parameter function may be used to establish predetermined acceptable limits of the parameter within the frequency band. | 04-15-2010 |
