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Fan, Hsinchu County
Arthur Fan, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100052285 | Integral Bicycle Frame - An integral bicycle frame includes a single-piece molded front frame unit with first and second joined regions, and a single-piece molded rear frame unit with upper and lower anchored regions which are respectively coupled with the first and second joined regions through upper and lower coupling joints. Each of the upper and lower coupling joints has a tubular socket blank and a plug blank which respectively have inner and outer tubular surfaces matingly fitted to each other. The inner and outer tubular surfaces of one of the coupling joints are configured to respectively diverge and converge toward each other so as to facilitate inter-engagement therebetween. | 03-04-2010 |
Cheng-Wen Fan, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100328022 | METHOD FOR FABRICATING METAL GATE AND POLYSILICON RESISTOR AND RELATED POLYSILICON RESISTOR STRUCTURE - An integrated method includes fabricating a metal gate and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a polysilicon structure of the polysilicon resistor. When the gate conductor of a poly gate transistor is etched, the part of the polysilicon structure is protected by the patterned photoresistor layer. After the polysilicon resistor and the metal gate are formed. The polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection. | 12-30-2010 |
| 20110073957 | METAL GATE TRANSISTOR WITH RESISTOR - A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures. | 03-31-2011 |
Chen-Jyh Fan, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100163570 | AUTOMATIC CARD DISPENSER - An automatic card dispenser is disclosed, which comprising: a base provided with a standby area, an output area, and a first track and second track parallel to each other; said standby area and output area are respectively provided on each end of the first track and second track, and each side of the dispensed card are respectively put in the first track and second track, and the first track is capable of separating from the standby area and output area; a vertical lifting unit connected to the base with a card box and a vertical driver; a horizontal pushing unit connected to the base for putting the card to contact card pressing wheel provided in the output area along the second track; and a recycling unit connected to the base and provided below the first track. | 07-01-2010 |
| 20110226860 | PRINTED CIRCUIT BOARD WITH ANTENNA FOR RFID CHIP AND METHOD FOR MANUFACTURING THE SAME - A printed circuit board with an antenna for an RFID chip and a method for manufacturing the printed circuit board are provided. The method includes steps of providing a printed circuit board whereon a metal foil layer is disposed; patterning the metal foil layer to form an antenna comprising a first antenna branch and a second antenna branch, wherein the first antenna branch has at least two right-angle turns; and mounting an RFID chip on the metal foil layer so as to be electrically connected to the first antenna branch and the second antenna branch, wherein a via hole is formed between the right-angle turns of the first antenna branch, so that the first antenna branch is electrically connected to a metal conductor inside or on the back of the printed circuit board through the via hole. | 09-22-2011 |
Chih-Yu Fan, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090052292 | Method and system for signal gain control in optical disc drives - A signal gain control method and system for use in optical disc drives to prevent undesirable saturation occurrences in circuit operations. The method includes fetching a preset reading front monitor diode signal and a preset gain controlling signal for reading; generating a front monitor diode signal by a front monitor diode signal conversion circuit; calculating a gain controlling signal based on the preset gain controlling signal for reading, the preset reading front monitor diode signal, and the front monitor diode signal by a signal processor; adjusting a gain for detection signals according to the gain controlling signal by a gain adjustment unit; and generating control signals according to the adjusted detection signals by a pre-amp module. | 02-26-2009 |
Chiu-Ting Fan, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20080274508 | Expression system for enhancing solubility and immunogeneicity of recombinant proteins - Expression system for enhancing solubility and immunogenicity of recombinant proteins. The expression system includes a protein expression vector that contains a chimeric gene encoding a chimeric protein. The chimeric protein contains three polypeptidyl fragments: (a) a first polypeptidyl fragment at the N-terminal end of the chimeric protein that contains a protein transduction domain (PTD) or a fragment thereof having HIV Tat PTD activity; (b) a second polypeptidyl fragment at the C-terminal end of the first polypeptidyl fragment that contains a J-domain or a fragment thereof having heat shock protein 70 (Hsp70)-interacting activity; and (c) a third polypeptidyl fragment at the C-terminal end of the second polypeptidyl fragment that contains a target protein or polypeptide. | 11-06-2008 |
| 20090187004 | EXPRESSION SYSTEM FOR ENHANCING SOLUBILITY AND IMMUNOGENEICITY OF RECOMBINANT PROTEINS - Expression system for enhancing solubility and immunogenicity of recombinant proteins. The expression system includes a protein expression vector that contains a chimeric gene encoding a chimeric protein comprising: (a) a first polypeptidyl fragment at the N-terminal end of the chimeric protein, containing a protein transduction domain (PTD), or a fragment thereof, having HIV Tat PTD activity; (b) a second polypeptidyl fragment at the C-terminal end of the first polypeptidyl fragment, containing a J-domain, or a fragment thereof, having heat shock protein 70 (Hsp70)-interacting activity; and (c) a third polypeptidyl fragment at the C-terminal end of the second polypeptidyl fragment, containing a target protein or polypeptide. | 07-23-2009 |
Chun-Sheng Fan, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20080199609 | APPARATUS AND METHOD FOR COMPENSATING UNIFORMITY OF FILM THICKNESS - An apparatus and a method for compensating uniformity of film thickness are provided. A shielding plate is provided between a vapor deposition object and a evaporation source. During the vapor deposition process, a shielding plate is continuously moved according to film deposition rates, so as to selectively pass or block atoms emitted from the evaporation source to achieve purpose of adjustably depositing. | 08-21-2008 |
| 20090009726 | MULTI-PRIMARY-COLOR DIGITAL LIGHT SPLITTING AND COMBINING SYSTEM AND METHOD, AND DIGITAL PROJECTOR - A multi-primary-color light splitting and combining system, includes a dichroic device, receiving an incident light beam and splitting into a first light beam having a first wavelength range and a second light beam having a second wavelength range. The first wavelength range in wavelength value is larger than the second wavelength range. A first polarized beam splitter receives the first light beam and splits out a first polarization beam having a first predetermined polarization state. A second polarized beam splitter receives the second light beam and splits out a second polarization beam having a second predetermined polarization state. A first and a second reflective displaying panels respectively receive the first and second polarization light beams, and reflect first and second sets of image information with respect to multiple primary colors. A polarized beam splitter combines first and second sets of image information to form an image light beam. | 01-08-2009 |
| 20110273633 | PROJECTION SYSTEM AND METHOD FOR ALTERNATELY OUTPUTTING DIFFERENT POLARIZED IMAGE LIGHT SOURCES - A projection system for alternately outputting different polarized image light sources includes a polarizing beam splitting module, an image display module and a light polarization switch module. The polarizing beam splitting module has at least one polarizing beam splitting element for intermittently receiving a plurality of input light sources according to different time sequences. The image display module has at least one reflective image display panel disposed beside a first side of the polarizing beam splitting element. The light polarization switch module has at least one transmission LCD light valve disposed beside a second side of the polarizing beam splitting element. Therefore, the image light sources with P polarization and the image light sources with S polarization can be intermittently and alternatively projected from the projection lens onto the surface of the object by switching the transmission LCD light valve to ON/OFF state according to different time sequences. | 11-10-2011 |
Jui-Fen Fan, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20080277651 | ORGANIC NON-VOLATILE MEMORY MATERIAL AND MEMORY DEVICE UTILIZING THE SAME - Disclosed is an organic non-volatile memory (ONVM) material including nanoparticles evenly dispersed in a first polymer. The nanoparticles have a metal core covered by a second polymer to form a core/shell structure, and the first polymer has a higher polymerization degree and molecular weight than the second polymer. The ONVM material of the invention has high uniformity, thereby stabilizing the electric properties of the memory device, such as increasing rewrite counts, increasing data retention time, reducing driving voltage, reducing write current, and enhancing current on/off ratio. | 11-13-2008 |
Ming-Chi Fan, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20080227249 | CMOS Image Sensor White Pixel Performance - Methods and systems for forming a photodiode in a substrate, forming a source/drain region in the substrate and extending over at least a portion of the photodiode, and growing a thermal oxide layer over the photodiode by performing a rapid thermal anneal (RTA) process utilizing an oxidizing environment. | 09-18-2008 |
Ming-Yu Fan, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100292824 | SYSTEM AND METHOD FOR IMPLEMENTING A WAFER ACCEPTANCE TEST ("WAT") ADVANCED PROCESS CONTROL ("APC") WITH NOVEL SAMPLING POLICY AND ARCHITECTURE - System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) are described. In one embodiment, the method comprises performing a key process on a sample number of wafers of a lot of wafers; performing a key inline measurement related to the key process to produce metrology data for the wafers; predicting WAT data from the metrology data using an inline-to-WAT model; and using the predicted WAT data to tune a WAT APC process for controlling a tuning process or a process APC process. | 11-18-2010 |
Shang-Chin Fan, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100053533 | SYSTEM FOR DISPLAYING IMAGES AND MANUFACTURING METHOD OF THE SAME - A system for displaying images and manufacturing method of the same are provided. The system for displaying images includes a liquid crystal display panel. The liquid crystal display panel includes a first substrate having a circuit pattern thereon. A second substrate is disposed to oppositely face the first substrate. A liquid crystal layer is sandwiched between the first and second substrates. A sealant is between the first and second substrates and adjacent to the liquid crystal layer. The circuit pattern has at least one light-transmitting area corresponding to the boundary between the sealant and the liquid crystal layer thereby allowing a light to irradiate the sealant. | 03-04-2010 |
Sheng-Po Fan, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090325517 | TRANSMITTING POWER LEVEL CONTROLLER AND RELATED METHOD - A transmitting power level controller of a communication system includes a radio-frequency unit for generating a communication signal and a power amplifier for amplifying the communication signal to generate a transmitting signal. The transmitting power level controller has a temperature sensor, a power detector, and an automatic level controller. The temperature sensor senses temperature of at least one of the RF unit and the PA to generate a detected temperature signal. The power detector detects a transmitting power of the transmitting signal to generate a detected power signal. The automatic level controller is coupled to the temperature sensor and the power detector. The power detector adjusts the transmitting power of the transmit signal according to the detected power signal when a maximal transmitting power is in a predetermined range, and adjusts the transmitting power according to the detected temperature signal otherwise. | 12-31-2009 |
Shu-Hui Fan, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20110061848 | Heat Dissipation Module and the Manufacturing Method Thereof - The present invention discloses a heat dissipation module and a manufacturing method thereof. The heat dissipation module comprises a metal base, a porous metal layer and a metal plate member. The porous metal layer is disposed on one side of the metal base and includes a plurality of micropores. Parts of the plurality of micropores contain a metal medium. The metal plate member is disposed on one side of the porous metal layer. Heat is rapidly conducted from the metal base through the metal plate member to the environment by means of the porous metal layer and the metal medium. | 03-17-2011 |
Ya-Ting Fan, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20120039129 | COST SAVING ELECTRICALLY-ERASABLE-PROGRAMMABLE READ-ONLY MEMORY (EEPROM) ARRAY - A cost saving electrically-erasable-programmable read-only memory (EEPROM) array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines are classified into a plurality of bit line groups, containing a first group bit lines; the word line includes a first and a second word lines; and the common source line includes a first common source line. And, a plurality of sub-memory arrays are provided. Each sub-memory array includes a first and a second memory cells disposed opposite to each other and located on two different sides of the first common source line; the first memory cell is connected to the first group bit lines, the first common source line, and the first word line, and the second memory cell is connected to the first group bit line, the first common source line, and the second word line. | 02-16-2012 |
| 20120039131 | LOW-VOLTAGE EEPROM ARRAY - A low-voltage EEPROM array, which has a plurality of parallel bit lines, parallel word lines and parallel common source lines is disclosed. The bit lines include a first bit line. The word lines include a first word line and a second word line. The common source lines include a first common source line and a second common source line. The low-voltage EEPROM array also has a plurality of sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell connects with the first bit line, the first common source line and the first word line. The second memory cell connects with the first bit line, the second common source line and the second word line. The first and second memory cells are symmetrical and arranged between the first and second common source lines. | 02-16-2012 |
| 20120040504 | METHOD FOR INTEGRATING DRAM AND NVM - The present invention discloses a method for integrating DRAM and NVM, which comprises steps: sequentially forming on a portion of surface of a DRAM semiconductor substrate a first gate insulation layer and a first gate layer functioning as a floating gate; and implanting ion into regions of the semiconductor substrate, which are at two sides of the first gate insulation layer, to form two heavily-doped areas that are adjacent to the first gate insulation layer and respectively function as a drain and a source; respectively forming over the first gate layer a second gate insulation layer and a second gate layer functioning as a control gate. The present invention not only increases the transmission speed but also reduces the power consumption, the fabrication cost and the package cost. | 02-16-2012 |
Yi-Hsuan Fan, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090110316 | APPARATUS AND METHOD FOR PERFORMING VIDEO DECODING PROCESSES IN PARALLEL - An apparatus and a method for performing video decoding processes in parallel are provided. The method is adapted for utilizing a first cluster and a second cluster of a processor to perform the video data decoding process in parallel. The method includes performing a VLD process to the video data with the first cluster, so as to obtain a plurality of coefficients and then performing an IZ process, an IQ process, and an IDCT process to the coefficients with the second cluster, so as to obtain a plurality of pixels values of the video data. When the first cluster decodes a coefficient of the video data, the second cluster performs the IZ, IQ, and IDCT processes to a coefficient previously decoded by the second cluster of the video data. Accordingly, a parallel process is realized and the decoding speed is increased. | 04-30-2009 |
| 20100235666 | METHOD FOR DETERMINING SWITCHING OF SLEEP MODE, COMPUTER PROGRAM PRODUCT FOR PERFORMING THE METHOD, AND RECORDING MEDIUM FOR THE COMPUTER PROGRAM PRODUCT - A method for determining switching of the sleep mode for a device is provided. The device and a base station have several connections therebetween. In the determining method, one of the connections is first provided and it is determined whether the connection is realtime or non-realtime. It is then determined whether or not the realtime and non-realtime connections satisfy the condition for entering the sleep mode according to a first condition and a second condition, respectively. If the connection does not satisfy the condition for entering the sleep mode, the device enters the normal mode. If the connection satisfies the condition for entering the sleep mode, then the foregoing steps are repeated till the connections have all been checked. If all of the connections satisfy the condition for entering the sleep mode, the device enters the sleep mode. | 09-16-2010 |
Yu-Ling Fan, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100292433 | SOLUBLE POLYTHIOPHENE DERIVATIVE - The invention discloses soluble polythiophene derivatives containing highly coplanar repeating units. The coplanar characteristic of side chain conjugated thiophene units improves the degree of the intramolecular conjugation and intermolecular π-π interaction. The polythiophene derivative exhibits good carrier mobility and is suitable for use in photo-electronic device such as organic thin film transistors (OTFT), organic light-emitting diodes (OLEDs), and organic solar cells (OSCs). | 11-18-2010 |
Zhen Hao Fan, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20120014087 | SIMPLE DETACHABLE ILLUMINATION STRUCTURE AND LAMP TUBE - A simple detachable illumination lamp tube includes a tube unit, a heat-dissipating unit, a light-emitting unit, a support unit and a lateral cover unit. The tube unit has a light-permitting hollow tube. The heat-dissipating unit has a heat-dissipating substrate received in the light-permitting hollow tube. The heat-dissipating substrate has two opposite lateral sides contacting the inner surface of the light-permitting hollow tube. The light-emitting unit has a plurality of strip light-emitting modules received in the light-permitting hollow tube. The strip light-emitting modules are disposed on the heat-dissipating substrate and electrically connected in sequence. The support unit has a plurality of support elements received in the light-permitting hollow tube and disposed between a bottom side of the heat-dissipating substrate and the inner surface of the light-permitting hollow tube. The lateral cover unit has two lateral covers installed on two ends of the light-permitting hollow tube. | 01-19-2012 |