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Fan, Hsinchu City
Chen-Lung Fan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120087120 | GRILLE LIGHT FIXTURE AND HOUSING THEREOF - A grille light fixture and its housing are provided. The grille light fixture includes a housing, at least one light emitting device and an optical film. The housing has a base plate, a surrounding wall upwardly extending from the base plate and a plurality of supporting members disposed at the top of the surrounding wall, wherein the surrounding wall defines an opening. The light emitting device, an LED device for example, is disposed on the base plate. The optical film, a diffusion plate for example, is fixed on the supporting members and covers the opening. | 04-12-2012 |
Chih-Hsun Fan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090168393 | Polarized light illumination device - A polarized light illumination device is described, which includes a light source, a polarizer, a reflector, and a polarized light converter. The light source generates light. The reflector is used for reflecting light generated by the light source towards the polarizer. The polarizer allows a first polarized light to pass through, and reflects a second polarized light. The polarized light converter reflects the light irradiated on the polarized light converter and performs a polarization conversion. A plane where the polarized light converter is located is substantially perpendicular to the polarizer. | 07-02-2009 |
| 20090311774 | BIOASSAY SYSTEM INCLUDING OPTICAL DETECTION APPARATUSES, AND METHOD FOR DETECTING BIOMOLECULES - A bioassay system is disclosed. The bioassay system may include a plurality of optical detection apparatuses, each of which includes a substrate having a light detector, and a linker site formed over the light detector, the linker site being treated to affix the biomolecule to the linker site. The linker site is proximate to the light detector and is spaced apart from the light detector by a distance of less than or equal to 100 micrometers. The light detector collects light emitted from the biomolecule within a solid angle of greater than or equal to 0.8 SI steridian. The optical detection apparatus may further include an excitation light source formed over the substrate so as to provide a light source for exciting a fluorophore attached to the biomolecule. | 12-17-2009 |
| 20100165451 | OPTICAL DEFLECTOR AND OPTICAL DEFLECTING BOARD - An optical deflector includes a substrate, an electrode layer on the substrate, an insulating layer at a predetermined peripheral region on the electrode layer, exposing the central region of the electrode layer. First electrode sandwiched wall is on the insulating layer. Second electrode sandwiched wall is on the insulating layer corresponding to the first electrode sandwiched wall. A pair of insulating walls is between the first electrode sandwiched wall and the second electrode sandwiched wall in enclosing to form an inner space. An outer wall encloses the pair of insulating layers, the first and the second electrode sandwiched walls at outside. A cap layer covers on the outer wall. A first liquid is filled into the inner space in contact with the electrode layer. A second liquid is filled into the inner spacer without solving to each other and forms a liquid interface. | 07-01-2010 |
Fu-Jier Fan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080211026 | Coupling well structure for improving HVMOS performance - A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric. | 09-04-2008 |
| 20090142898 | Coupling Well Structure for Improving HVMOS Performance - A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric. | 06-04-2009 |
Hsiang-Pin Fan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100085525 | THIN FILM TRANSISTOR SUBSTRATE, LIQUID CRYSTAL PANEL AND LIQUID CRYSTAL DISPLAY DEVICE USING THE SAME - A thin film transistor (TFT) substrate including a base, a plurality of scan lines and data lines and a pixel unit is provided. The scan lines are disposed on the base. The data lines are disposed above the scan lines and are perpendicular to the scan lines to define a plurality of pixel areas. The pixel unit is disposed on the base and inside one of the pixel areas. The pixel unit comprises a TFT and a pixel electrode. The TFT comprises a source and a drain. The pixel electrode is electrically connected to the drain. The pixel electrode comprises a first main electrode, a second main electrode and a plurality of branch electrodes. The first main electrode is perpendicular to the second main electrode. The branch electrodes are connected to the first main electrode and/or the second main electrode. The first main electrode substantially divides the pixel area evenly. | 04-08-2010 |
| 20100118252 | ACTIVE DEVICE ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL - An active device array substrate includes a substrate, a pixel array, a peripheral circuit, and a number of marks. The substrate has an active area and a peripheral circuit area that is connected to the active area. The pixel array is disposed on the active area of the substrate. The peripheral circuit is disposed on the peripheral circuit area of the substrate. Besides, the peripheral circuit includes a number of driver bonding pads, a number of fan-out lines, and a number of connecting lines. The fan-out lines are electrically connected to the pixel array. Each of the connecting lines connects one of the driver bonding pads and one of the fan-out lines. Additionally, the connecting lines are arranged in different pitches. Each of the marks is disposed between two adjacent connecting lines. | 05-13-2010 |
Ming-Chi Fan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080293222 | METHOD FOR FORMING SILICON-GERMANIUM EPITAXIAL LAYER - A method for forming a SiGe epitaxial layer is described. A first SEG process is performed under a first condition, consuming about 1% to 20% of the total process time for forming the SiGe epitaxial layer. Then, a second SEG process is performed under a second condition, consuming about 99% to 80% of the total process time. The first condition and the second condition include different temperatures or pressures. The first and the second SEG processes each uses a reactant gas that includes at least a Si-containing gas and a Ge-containing gas. | 11-27-2008 |
Shieng Chiang Fan, Hsinchu City TW
Tso-Hung Fan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100033884 | ESD PROTECTION TRIGGER CIRCUIT - This invention discloses a trigger circuit for an electrostatic discharge (ESD) protection device, the ESD protection device being turned on during an ESD event and being turned off during a normal operation, the trigger circuit comprises a voltage sensing circuit coupled to a bonding pad, the voltage sensing circuit being configured to produce a first predetermined voltage during a ESD event, and to produce a second predetermined voltage complimentary to the first predetermined voltage during a normal operation, and a voltage converting circuit having a positive feedback circuit and coupled between the voltage sensing circuit and the ESD protection device for converting the first predetermined voltage to a third predetermined voltage for turning on the ESD protection device, and for converting the second predetermined voltage to a fourth predetermined voltage for turning off the ESD protection device. | 02-11-2010 |
Tzu-Chung Fan, Hsinchu City TW
Wei-Han Fan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120108026 | METHOD OF MANUFACTURING STRAINED SOURCE/DRAIN STRUCTURES - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region. | 05-03-2012 |
Yang-Tung Fan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090111208 | COLORS ONLY PROCESS TO REDUCE PACKAGE YIELD LOSS - Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon. A transparent encapsulant is deposited to planarize the color filter layer and completes the solid-state color image-forming device without conventional convex microlenses. | 04-30-2009 |
Yuh-Da Fan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100099252 | Methods to completely eliminate or significantly reduce defects in copper metallization in IC manufacturing - A method for the improved electroplating of copper onto a copper seed layer provides burnishing the surface of the copper seed layer. The burnishing treatment is used to enhance the platability of the copper seed layer. The burnishing may be a reverse electroplating or a sputter etching process. Following the burnishing of the seed layer, the copper layer that is electroplated onto the seed layer exhibits improved quality. | 04-22-2010 |
Yu-Wen Fan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110297434 | VACUUM HERMETIC ORGANIC PACKAGING CARRIER - A vacuum hermetic organic packaging carrier is provided. The organic packaging carrier includes an organic substrate, a conductive circuit layer, and an inorganic hermetic insulation film. The organic substrate has a first surface. The conductive circuit layer is located on the first surface and exposes a portion of the first surface. The inorganic hermetic insulation film at least covers the exposed first surface to achieve an effect of completely hermetically sealing the organic packaging carrier. | 12-08-2011 |