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Faltermeier
Claire Faltermeier, Los Angeles, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120087914 | INHIBITION OF TRIM62 ACTIVITY REDUCES CANCER CELL PROLIFERATION - The present invention provides methods to treat cancers using inhibitors of the TRIM62 protein and methods to identify inhibitors and other modulators of the TRIM62 protein. Pharmaceutical compositions that contain an inhibitor of a TRIM62 protein are also provided. | 04-12-2012 |
Johnathan Faltermeier, Delanson, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090230471 | TRENCH MEMORY WITH SELF-ALIGNED STRAP FORMED BY SELF-LIMITING PROCESS - A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material. | 09-17-2009 |
| 20100102373 | TRENCH MEMORY WITH SELF-ALIGNED STRAP FORMED BY SELF-LIMITING PROCESS - A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material. | 04-29-2010 |
Johnathan E. Faltermeier, Albany, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100207245 | HIGHLY SCALABLE TRENCH CAPACITOR - An improved trench structure, and method for its fabrication are disclosed. Embodiments of the present invention provide a trench in which the collar portion has an air gap instead of a solid oxide collar. The air gap provides a lower dielectric constant. Embodiments of the present invention can therefore be used to make higher-performance devices (due to reduced parasitic leakage), or smaller devices, due to the ability to use a thinner collar to achieve the same performance as a thicker collar comprised only of oxide (with no air gap). Alternatively, a design choice can be made to achieve a combination of improved performance and reduced size, depending on the application. | 08-19-2010 |
| 20110092069 | SELF-ALIGNED PATTERNED ETCH STOP LAYERS FOR SEMICONDUCTOR DEVICES - A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material. | 04-21-2011 |
| 20110108920 | HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE - A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure. | 05-12-2011 |
| 20110175164 | DEVICE STRUCTURE, LAYOUT AND FABRICATION METHOD FOR UNIAXIALLY STRAINED TRANSISTORS - A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices. | 07-21-2011 |
| 20110227165 | HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE - A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure. | 09-22-2011 |
| 20110254015 | METHOD FOR IMPROVING DEVICE PERFORMANCE USING EPITAXIALLY GROWN SILICON CARBON (SiC) OR SILICON-GERMANIUM (SiGe) - A semiconductor substrate including a field effect transistor (FET) and a method of producing the same wherein a stressor is provided in a recess before the source/drain region is formed. The device has an increased carrier mobility in the channel region adjacent to the gate electrode. | 10-20-2011 |
Johnathan E. Faltermeier, Lagrangeville, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090108306 | UNIFORM RECESS OF A MATERIAL IN A TRENCH INDEPENDENT OF INCOMING TOPOGRAPHY - Columnar elements which extend to varying heights above a major surface of a substrate, e.g., polysilicon studs within trenches in the substrate, are recessed to a uniform depth below the major surface. The columnar elements are etched selectively with respect to a material exposed at the surface in an at least partly lateral direction so that the columnar elements are recessed to a uniform depth below the major surface at walls of the trenches. | 04-30-2009 |
Johnathan E. Faltermeier, Fishkill, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090072355 | DUAL SHALLOW TRENCH ISOLATION STRUCTURE - A protective dielectric layer is formed on a first shallow trench having straight sidewalls, while exposing a second shallow trench. An oxidation barrier layer is formed on the semiconductor substrate. A resist is applied and recessed within the second shallow trench. The oxidation barrier layer is removed above the recessed resist. The resist is removed and thermal oxidation is performed so that a thermal oxide collar is formed above the remaining oxidation mask layer. The oxidation barrier layer is thereafter removed and exposed semiconductor area therebelow depth is etched to form a bottle shaped shallow trench. The first and the bottle shaped trenches are filled with a dielectric material to form a straight sidewall shallow trench isolation structure and a bottle shallow trench isolation structure, respectively. Both shallow trench isolation structures may be employed to provide optimal electrical isolation and device performance to semiconductor devices having different depths. | 03-19-2009 |
Ralf Faltermeier, Heidenrod DE
| Patent application number | Description | Published |
|---|---|---|
| 20090136696 | Printing Ink System For Printing On Polyamide-Based Food Casings, Printed Food Casings And Process For Their Production - A one-ply or multi-ply food casing based on (co)polyamide, or which has an outer ply based on (co)polyamide, is disclosed that is printed with a printing ink cured by a free radical mechanism. The printing ink is printed on a layer of a base ink which also cures by a free radical mechanism. The base ink contains, in one and the same molecule, at least one group which can form a bond with the (co)polyamide surface, in particular an isocyanate group, and at least one ethylenically unsaturated group which can undergo a free radical polyaddition reaction, in particular a (meth)acrylate group. The print adheres firmly on the casing and is abrasion- and scratch-resistant, even without additional varnish. | 05-28-2009 |