Patent application number | Description | Published |
20080259630 | LENS ASSEMBLY - A lens assembly for use with a light source and including an inner lens and a light directing portion. The inner lens collects light rays from the light source through a light-collecting face and emits at least a portion of the light rays radially through a series of collimators. The light directing portion may be an outer lens having light-collecting faces and light-distributing faces. The light-collecting faces correspond with the collimators and distribute the light rays through light-distributing faces. The light direction portion may alternatively be an outer reflector. The reflector has a plurality of light-reflecting surfaces, corresponding to the collimators, and configured to reflect the light rays emitted from the collimators. | 10-23-2008 |
20080304277 | INCREASED EFFICIENCY LED PROJECTOR OPTIC ASSEMBLY - A projector optic assembly for generating and projecting a high gradient beam. The assembly includes a light pipe defining an optical axis and having a collection unit, a funneling unit, and an emitting surface. The collection unit extends from a first end to a transition plane defining the transition from the collection unit to the funneling unit. The collection unit is configured to collect light from a source and direct it through the transition plane, whereafter the funneling unit extends from the transition plane to the emitting surface. The emitting surface has an area smaller than an area of the transition plane selected to increase the efficiency of the funneling unit. Spaced apart from and generally opposite of the emitting surface is a condenser lens | 12-11-2008 |
20090196047 | REMOTELY LIT OPTICAL SIGNATURE LAMP - A lighting system and a method for providing a lighting pattern are disclosed, wherein the lighting system and method minimize non-uniform color and intensity in the lighting pattern, offers unique styling features, and provides design flexibility for the LED package and associated heatsinking devices. The lighting system including a light source, a first light bending device disposed adjacent the light source and adapted to receive light rays emitted from the light source and direct the light rays in a first desired lighting pattern, and a second light bending device disposed around the first light bending device, wherein the optical device is adapted to receive the directed light rays from the first light bending device and direct the light rays in a second desired lighting pattern. | 08-06-2009 |
20120104951 | SYSTEM AND METHOD FOR REDUCING LAMP RESTRIKE TIME - Systems and methods for reducing lamp restrike time are provided. In a lighting apparatus having a housing, a reflector, and a lamp positioned so that at least a portion of the outer jacket of the lamp is within the reflector, a circulating device is operated when the lamp is off and a temperature inside the housing is above a predefined temperature. The circulating device circulates air around the outer jacket of the lamp to cool the lamp so the restrike time is reduced without the need for a starting device with a starting voltage high enough to restart the lamp when the lamp is hot. | 05-03-2012 |
Patent application number | Description | Published |
20090080413 | IP Telephone System - An Internet Protocol (IP) telephone has a constant impedance filter that is capable of being continuously attached to the physical layer of a computer chip in the IP telephone. The constant impedance filter is located outside the physical layer and is connected to a relay on the physical layer. The relay is configured using native FET devices, which are normally conductive without a supply voltage. Therefore, the relay is capable of operating during the discovery mode of IP telephone operation, where no power is applied to the substrate. Rectifier circuits rectify an incoming signal during discovery mode, and apply the rectified signal to the gate of the relay to improve conductivity of the relay. This allows for faster detection of the IP telephone during discovery mode. During normal operation mode, voltage is applied to the physical layer, and the relay is opened by grounding the native devices. Also, during the normal operation mode, any signal coming from the constant impedance filter is terminated in a switchable termination resistor that is also disposed on the physical layer. | 03-26-2009 |
20100067521 | Internet protocol telephone system - An internet protocol telephone includes a substrate having an input and an output that are capable of being connected to the internet protocol (IP) network. A relay is disposed on the substrate and is connected between the input and the output of the substrate. The relay includes first and second native FETs that have a threshold voltage of approximately zero volts. Therefore, the relay is nominally turned-on, even when little or no voltage (or power) is applied to the IP telephone substrate, as during the discovery mode of IP telephone operation. During discovery mode, The IP phone is configured to be responsive to extended link pulses and block data packets that are associated with legacy devices. Data packets have a higher signal duration and are more continuous than extended link pulses. The IP phone includes a switchable ground that is connected to the gates of the native devices, and is controlled by a rectifier and filter circuit that are connected to the substrate input. If the IP phone receives legacy data packets during discovery mode, then the high signal duration and continuous nature of the data packets are sufficient to cause the rectifier to generate a rectified signal having sufficient amplitude to activate the switchable ground, so as to ground the gates of the native devices and therefore turn-off the native devices. Therefore, the data packets are rejected and are not passed back to the switch. Extended link pulses have a frequency that is too low to generate a rectified signal that is sufficient to activate the switchable ground, and therefore the native devices remain turned-on. Accordingly, the extended link pulses are passed back to the switch. | 03-18-2010 |
20120223765 | Method and System for Passive Signal Detector for Chip Auto Power on and Power Down - While an IC chip is in idle mode with no power being supplied to the IC chip, the IC chip may be operable to detect a signal pulse received by the IC chip using energy associated with the signal pulse. The IC chip may be operable to control a control signal for a power switch using the energy associated with the signal pulse. The power switch may allow power to be provided to the IC chip based on the control signal. The IC chip may comprise a pulse detector, a latch circuit and an ON/OFF logic circuit within the IC chip. While the IC chip is fully powered and communication with a partner chip is finished, the IC chip may be operable to control the control signal to turn off the power switch for powering down the IC chip based on a turn-off signal. | 09-06-2012 |
20120313714 | Reference-Less Voltage Controlled Oscillator (VCO) Calibration - Embodiments for reference-less voltage controlled oscillator (VCO) calibration are provided. Embodiments include a VCO calibration module which uses one or more signals from a frequency detector to automatically select a proper VCO band and bring the VCO clock frequency close enough to the data rate. The VCO calibration module uses a calibration code to calibrate the VCO. In embodiments, the calibration code is determined using a frequency search scheme, which includes a discovery phase to determine the proper VCO band, and a binary search phase and a monitoring phase to select the calibration code that brings the VCO clock frequency closest to the data rate. | 12-13-2012 |
20120313715 | Reference-Less Frequency Detector - Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal. | 12-13-2012 |
20130285752 | Reference-Less Frequency Detector - Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal. | 10-31-2013 |
20140126614 | SYSTEM, METHOD, AND APPARATUS FOR DIGITAL PRE-EMPHASIS IN LOW POWER SERDES SYSTEMS - A communication system is described that includes a transmitter to transmit data using one or more drivers. The drivers may drive the data in a manner that accords with pre-emphasis being selectively enabled or disabled for each driver. The pre-emphasis, when enabled, is applied by corresponding driver. The drivers may also be programmably selected and enabled or disabled. The transmitter also includes one or more driver selection circuits. The driver selection circuits may be configured to select one or more of the drivers to transmit the data, to selectively enable or disable pre-emphasis to be applied by each of the selected drivers, and to provide the data, or representations thereof, to the selected drivers. | 05-08-2014 |
20140241442 | COMPACT LOW-POWER FULLY DIGITAL CMOS CLOCK GENERATION APPARATUS FOR HIGH-SPEED SERDES - A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another. | 08-28-2014 |
20150180649 | COMPACT LOW-POWER FULLY DIGITAL CMOS CLOCK GENERATION APPARATUS FOR HIGH-SPEED SERDES - A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles. | 06-25-2015 |