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| 20090237161 | QUADRATURE OUTPUT LOW NOISE TRANSCONDUCTANCE AMPLIFIER HAVING DIFFERENTIAL INPUT - A device for providing low noise transconductance amplification is presented. The device includes a PMOS transconductance section configured to receive a differential RF input signal, a PMOS cascode section coupled to the PMOS transconductance section, an NMOS transconductance section configured to receive the RF differential input signal, and an NMOS cascode section coupled to the NMOS transconductance section, where the PMOS and NMOS cascode sections provide a differential quadrature output signal and a differential in-phase output signal. A method for amplifying an RF signal is also presented. The method includes receiving a differential RF input signal, converting the differential RF input signal into current signals, buffering the current signals to provide a differential quadrature output signal and a differential in-phase output signal. | 09-24-2009 |
| 20090284285 | SWITCHED-CAPACITOR DECIMATOR - A switched-capacitor decimator that can attenuate undesired signal components at odd harmonics of an output sample rate is described. In one design, the switched-capacitor decimator includes at least one sampling capacitor and multiple switches. For each sampling capacitor, the top plate is charged with a first input signal when the capacitor is selected for top charging, and the bottom plate is charged with a second input signal when the capacitor is selected for bottom charging. For each sampling capacitor, the top plate provides its stored charges to a first output signal and the bottom plate provides its stored charges to a second output signal when the capacitor is selected for reading. The switches couple the at least one sampling capacitor to the first and second input signals for charging and to the first and second output signals for reading. | 11-19-2009 |
| 20100225419 | PASSIVE SWITCHED-CAPACITOR FILTERS - A passive switched-capacitor (PSC) filter includes (i) an array of capacitors that can store and share electrical charge and (ii) an array of switches that can couple the capacitors to a summing node. Each switch couples an associated capacitor to the summing node when enabled. Each capacitor stores a voltage value from the summing node when selected for charging and shares electrical charge with other capacitors via the summing node when selected for charge sharing. The PSC filter may include multiple sections for multiple filter taps. Each section includes one or more capacitors of equal size determined based on a corresponding filter coefficient. The capacitors in each section may be sequentially selected for charging with an input or output signal, one capacitor in each clock cycle. In each clock cycle, one capacitor in each section may be selected for charge sharing to generate the output signal. | 09-09-2010 |
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| 20100327965 | RECEIVER FILTERING DEVICES, SYSTEMS, AND METHODS - Exemplary embodiments of the invention disclose receiver baseband filtering. In an exemplary embodiment, the filter device may comprise a continuous-time filter and a discrete-time filter operably coupled to the continuous time-filter. The discrete-time filter may include a passive infinite impulse response filter operably coupled between the continuous-time filter and an amplifier. The discrete-time filter may also include an active infinite impulse response filter operably coupled between an output of the amplifier and an input of the amplifier. The discrete-time filter may be configured to combine an output of the active infinite impulse response filter and an output of the passive infinite impulse response filter to form a composite signal. Furthermore, the amplifier may be configured to receive and amplify the composite signal. | 12-30-2010 |
| 20110043291 | DYNAMIC LIMITERS FOR FREQUENCY DIVIDERS - Techniques for generating quadrature signals from a local oscillator signal, wherein the generated quadrature signals have a frequency half of the local oscillator frequency. In an exemplary embodiment, two oscillators, e.g., injection locked oscillators, are provided, each oscillator having a load, a cross-coupled transistor pair, an integrating capacitor, and current injection transistors. A differential pair is coupled to the leads of each of the integrating capacitors, and the drains of the differential pair are coupled to the outputs of the other oscillator to help increase the slew rate of the output voltages of the other oscillator. The inputs to the differential pair may be first amplified to improve the gain of the differential pair. In another exemplary embodiment, the power consumption of the differential pair may be reduced by operating them in a discontinuous mode, e.g., by coupling the source voltages of the differential pair to corresponding delayed versions of the drain voltages. | 02-24-2011 |
| 20110050296 | DIVIDE-BY-TWO INJECTION-LOCKED RING OSCILLATOR CIRCUIT - A frequency divider involves a plurality of Injection-locked Ring Oscillators (ILRO). A first ILRO includes a pair of cross-coupled N-channel transistors, a pair of load resistors, an integrating capacitor, and a current injection circuit. The drain of each transistor is coupled to the gate of the other transistor. Each load resistor couples the drain of each transistor to a circuit voltage source. The integrating capacitor couples the sources of each transistor. The current injection circuit alternately opens and closes a path from the source of each transistor to circuit ground in response to an oscillatory input signal of a first frequency. In response, the voltage state at the drain of each transistor is alternately latched and toggled, generating a differential pair of oscillating signals frequency divided by two. A first and second ILRO driven in antiphase generate two differential output signals in phase quadrature. | 03-03-2011 |
