| Patent application number | Description | Published |
|---|
| 20090091988 | Writing bit alterable memories - A bit alterable memory may include current generators in a periphery outside the main memory core. Current may be generated in the periphery and driven into the core. As a result, the capacitance of the memory cells has a lowered effect. The current may be generated using the chip supply voltage and then mirrored using a pump voltage. In some embodiments, the mirroring may be ratioed at the partition level and multiplied at the plane level. A delay may be provided before applying the currents to the cell to accommodate for transients. | 04-09-2009 |
| 20090161417 | Two cell per bit phase change memory - A phase change memory array may have a plurality of cells in which a bit is determined by a single cell. In addition, a portion of the array may include a plurality of cells which are combined so that two cells form one bit of memory. One of the combined cells is programmed to the complementary state of the other of the combined cells. Thus, the bit is determined by reading the indicator bit which is correctly programmed and comparing it to the complement cell. As a result, the bit may be very reliable because the read window is twice as wide as that used in a conventional phase change memory which compares the selected bit current to a reference current that is midway between the programmed and unprogrammed states. | 06-25-2009 |
| 20090168503 | Phase change memory with bipolar junction transistor select device - A phase change memory may be organized with a global word line coupled to a plurality of blocks, each with a plurality of phase change memory cells arranged in rows and columns. Thus, one global word line may be common to a plurality of blocks. The global word line may be coupled to a word line decoder that is responsible for pulling the word line to ground. Each of the blocks, on the other hand, is coupled to a bitline selector through a bitline. Each block may have its own local word line coupled to the global word line. In some cases, this architecture reduces the minimum capacity of the memory. | 07-02-2009 |
| 20090196092 | Programming bit alterable memories - Program failures during programming can be corrected during reading using an error correcting code. This allows an array to pass programming more readily, speeding the operation of the memory and avoiding the need to continually reprogram or to issue an error message that the programming was unsuccessful. This makes the memory more user friendly and robust. | 08-06-2009 |
| 20100165714 | METHOD OF STORING AN INDICATION OF WHETHER A MEMORY LOCATION IN PHASE CHANGE MEMORY NEEDS PROGRAMMING - A phase change memory includes a float buffer which stores the result of a comparison between the current state of data in the phase change memory cells and an intended next state of each of those cells. The float buffer indicates which cells need to be programmed in order to achieve the new states and which cells happen to already be in the new states. Then, after programming of the cells, the float buffer indicates which cells still need to be programmed. Thus, a control stage uses the information in the float buffer to program only those cells whose states need to be changed. | 07-01-2010 |
| 20110085372 | NON-VOLATILE SRAM CELL THAT INCORPORATES PHASE-CHANGE MEMORY INTO A CMOS PROCESS - A SRAM cell having two cross-coupled inverters formed by CMOS technology and first and second chalcogenic elements integrated with the SRAM cell to add nonvolatile properties to the storage cell. The PCM resistors are programmed to the SET state and the RESET state, and upon power-up the SRAM cell takes on the data contained in the PCM cells. | 04-14-2011 |
