| Patent application number | Description | Published |
|---|
| 20080203379 | ARRAY OF VERTICAL BIPOLAR JUNCTION TRANSISTORS, IN PARTICULAR SELECTORS IN A PHASE CHANGE MEMORY DEVICE - A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions of dielectric material are formed in a semiconductor body, thereby defining a plurality of active areas, insulated from each other and a plurality of bipolar transistors are formed in each active area. In particular, in each active area, a first conduction region is formed at a distance from the surface of the semiconductor body; a control region is formed on the first conduction region; and, in each control region, at least two second conduction regions and at least one control contact region are formed. The control contact region is interposed between the second conduction regions and at least two surface field insulation regions are thermally grown in each active area between the control contact region and the second conduction regions. | 08-28-2008 |
| 20090014709 | PROCESS FOR MANUFACTURING AN ARRAY OF CELLS INCLUDING SELECTION BIPOLAR JUNCTION TRANSISTORS WITH PROJECTING CONDUCTION REGIONS - A process manufactures an array of cells in a body of semiconductor material wherein a common conduction region of a first conductivity type and a plurality of shared control regions, of a second conductivity type, are formed in the body. The shared control regions extend on the common conduction region and are laterally delimited by insulating regions. Then, a grid-like layer is formed on the body to delimit a first plurality of empty regions directly overlying the body and conductive regions of semiconductor material and the first conductivity type are formed by filling the first plurality of empty regions, each conductive region forming, together with the common conduction region and an own shared control region, a bipolar junction transistor. | 01-15-2009 |
| 20100059829 | PROCESS FOR MANUFACTURING A MEMORY DEVICE INCLUDING A VERTICAL BIPOLAR JUNCTION TRANSISTOR AND A CMOS TRANSISTOR WITH SPACERS - A bipolar selection transistor and a circuitry MOS transistor for a memory device are formed in a semiconductor body. The bipolar selection transistor is formed by implanting a buried collector, implanting a base region on the buried collector, forming a silicide protection mask on the semiconductor body, and implanting an emitter region and a control contact region. The circuitry MOS transistor is formed by defining a gate on the semiconductor body, forming lateral spacers on the sides of the gate and implanting source and drain regions on the sides of the lateral spacers. Then, a silicide region is formed on the emitter, base contact, source and drain regions and the gate, in a self-aligned way. The lateral spacers are multilayer structures including at least two different layers, one of which is used to form the silicide protection mask on the bipolar selection transistor. Thereby, the dimensions of the lateral spacers are decoupled from the thickness of the silicide protection mask. | 03-11-2010 |
| 20100078619 | RESISTIVE MEMORY CELL AND METHOD FOR MANUFACTURING A RESISTIVE MEMORY CELL - A resistive memory cell includes a structural layer, a pore in the structural layer, a selector, having a coupling terminal accommodated in the pore, and a storage element of a resistive memory material, arranged in the pore and electrically coupled to the coupling terminal of the selector. The storage element has a tubular portion, extending transversely to an electrical coupling interface of the coupling terminal. | 04-01-2010 |
| 20100163827 | FORMING PHASE CHANGE MEMORY CELLS - Small phase change memory cells may be formed by forming a segmented heater over a substrate. A stop layer may be formed over the heater layer and segmented with the heater layer. Then, sidewall spacers may be formed over the segmented heater to define an aperture between the sidewall spacers that may act as a mask for etching the stop layer over the segmented heater. As a result of the etching using the sidewall spacers as a mask, sublithographic pore may be formed over the heater. Phase change material may be formed within the pore. | 07-01-2010 |
| 20100163833 | ELECTRICAL FUSE DEVICE BASED ON A PHASE-CHANGE MEMORY ELEMENT AND CORRESPONDING PROGRAMMING METHOD - A fuse device has a fuse element provided with a first terminal and a second terminal and an electrically breakable region, which is arranged between the first terminal and the second terminal and is configured to undergo breaking as a result of the supply of a programming electrical quantity, thus electrically separating the first terminal from the second terminal. The electrically breakable region is of a phase-change material, in particular a chalcogenic material, for example GST. | 07-01-2010 |
| 20100308296 | PHASE CHANGE MEMORY CELL WITH SELF-ALIGNED VERTICAL HEATER - A self-aligned vertical heater element is deposited directly on the silicide of a selection device, and a phase change chalcogenide material is deposited directly on the vertical heater element. The fabrication process allows for self-alignment between the chalcogenide line and vertical heater element. In an embodiment, the vertical heater element is L-shaped, having a vertical wall along the wordline direction and a horizontal base. The vertical wall and the horizontal base may have the same thickness. | 12-09-2010 |
| 20110141799 | REVERSING A POTENTIAL POLARITY FOR READING PHASE-CHANGE CELLS TO SHORTEN A RECOVERY DELAY AFTER PROGRAMMING - A potential supplied to selected cells in a Phase Change Memory (PCM) is reversed in polarity following a program operation to suppress a recovery time and provide device stabilization for a read operation. | 06-16-2011 |
