| Patent application number | Description | Published |
|---|
| 20080256284 | Simulation Circuit of Pci Express Endpoint and Downstream Port for a Pci Express Switch - Single hardware subsystems that present two software views that appear to be two separate hardware subsystems attached in a hierarchy are implemented with PCI-type arrangements. According to an example embodiment of the present invention, a hardware arrangement is adapted to emulate two virtually separate hierarchical subsystems in a single hardware block. This emulation facilitates the coupling of devices to PCI Express-type communications links while addressing PCI-Express-type linking requirements for such devices. | 10-16-2008 |
| 20090043931 | AUTOMATIC CONFIGURATION OF A COMMUNICATION PORT AS TRANSMITTER OR RECEIVER DEPENDING ON THE SENSED TRANSFER DIRECTION OF A CONNECTED DEVICE - A communications port is implemented for configuration in direction and arrangement. According to an example embodiment of the present invention, a communications link, such as a PCI Express type link, is configurable for communicating with devices having different directional and/or polarity configurations. The communications link is configured to match a communications port condition (e.g., a directional and/or polarity condition) of a device coupled to the communications link. In one instance, the communications link is directionally configurable for reassigning input lanes to output lanes and output lanes to input lanes. With this approach, the communications link can be used to communicate with a variety of devices having varied communication characteristics. | 02-12-2009 |
| 20090222705 | DATA PROCESSOR SYSTEM AND A METHOD FOR COMMUNICATION DATA - A data processor system is described comprising a first and a second data processor unit (PU | 09-03-2009 |
| 20100107008 | TRANSMISSION METHOD, TRANSMITTER AND DATA PROCESSING SYSTEM COMPRISING A TRANSMITTER - A method for transmitting data is described that includes the steps of: Producing a data frame for transmission, the data frame including a sequence number and user data, saving a copy of the data frame in a retransmission buffer, and if said step of saving a copy requires that data already present in the retransmission buffer is overwritten, selecting the one or more oldest data frames in the retransmission buffer to be overwritten, in case an error is determined in the received data frame, communicating an error message to the transmitter of the data frame, which error message at least comprises an indication of the sequence number of the last correctly received data frame—upon receipt of such message and if available, retransmitting one or more data frames from the retransmission buffer having a sequence number higher than the sequence number communicated in the message. | 04-29-2010 |
| 20100308897 | POWER ISLAND WITH INDEPENDENT POWER CHARACTERISTICS FOR MEMORY AND LOGIC - A power island for a system-on-a-chip (SoC) includes a first segment, a second segment, and a supply line. The first segment includes a hardware device and operates the hardware device at first power characteristics indicative of at least a first voltage. The second segment includes scalable logic and operates the scalable logic at second power characteristics indicative of at least a second voltage. The second power characteristics of the scalable logic are different from the first power characteristics of the hardware device. The supply line receives an external supply signal (VDD) and directs the external supply signal to both the first segment and the second segment. The second segment changes at least one power characteristic of the external supply signal to operate the scalable logic according to the second power characteristics. | 12-09-2010 |
| Patent application number | Description | Published |
|---|
| 20120137025 | Communication Bus with Shared Pin Set - Bus communications are effected. In accordance with one or more example embodiments, a bus circuit is configured for communicating data in accordance with a main protocol (e.g., as a default), and for communicating with an alternate protocol when signals corresponding to the main protocol are not present. In some implementations, a sense circuit is used with input pins to sense a type of signal for bus communications, and to control communications on the bus with a protocol appropriate for the sensed signals, and for a main protocol when main protocol signals are sensed (e.g., for a default bus operation, or for test operation). | 05-31-2012 |
| 20120137031 | COMMUNICATION BUS WITH SHARED PIN SET - Bus communications are effected. In accordance with one or more example embodiments, a bus circuit is configured for communicating data in accordance with a main protocol (e.g., as a default), and for communicating with an alternate protocol when signals corresponding to the main protocol are not present. In some implementations, a sense circuit is used with input pins to sense a type of signal for bus communications, and to control communications on the bus with a protocol appropriate for the sensed signals, and for a main protocol when main protocol signals are sensed (e.g., for a default bus operation, or for test operation). | 05-31-2012 |
