Patent application number | Description | Published |
20080270763 | Device and Method for Processing Instructions - A method and a device for processing instructions. The device includes a pipelined processor, an instruction memory unit and a register file, whereas the pipelined processor includes a write-back unit and an execution unit. The device is characterized by including a controller that is adapted to receive a first register group size information and a first register identification information that define a first group of source registers associated with a first instruction; and to determine an execution related operation of the first instruction in response to the first register group size information, the first register identification information, a second register group size information and a second register identification information. Whereas the second register group size information and the second register identification information define a second group of target registers associated with a second instruction. Whereas the second instruction is provided to the pipelined processor before the first instruction. | 10-30-2008 |
20080281778 | Hardware Accelerator Based Method and Device for String Searching - A method for searching within a data block for a data chunk having a predefined value, the method includes: fetching, by a processor, a data block search instruction; fetching, a data unit that includes multiple data chunks; wherein at least one data chunk within the data unit belongs to the data block; deciding whether to use a mask for data chunk level masking; searching, by a hardware accelerator, for a valid data chunk within the fetched data unit that has the predefined value; wherein the searching comprising applying a mask; wherein a valid data chunk in an non-masked data chunk that belongs to the data block; and determining whether to update the value of the mask and whether to fetch a new data unit that belongs to the data block. | 11-13-2008 |
20090006822 | Device and Method for Adding and Subtracting Two Variables and a Constant - A method device and a method. The method includes fetching an instruction, decoding an instruction that includes an instruction type field, a first variable field, a second variable field, a result field and a constant field; selecting an operation out of addition operation, a subtraction operation and another type of operation, in response to the content of the instruction type field; determining, in response to the value of the constant field, whether the result of the selected operation is responsive to the first and second variables or is responsive to the first variable, the second variable and the constant; and executing the selected operation, during a single instruction execution cycle, to provide the result. | 01-01-2009 |
20090070555 | DEVICE AND METHOD FOR FINDING EXTREME VALUES IN A DATA BLOCK - A method for locating an extreme value data chunk within a data block, the method includes: fetching, by a processor, an instruction; fetching, in response to a content of the instruction, a data unit that comprises multiple data chunks; selectively masking the fetched data chunks in response to a value of a mask; comparing, by a hardware accelerator, between values of valid data chunks to provide a extreme value data chunk; wherein valid data chunks include un-masked data chunks that belong to the data block; updating the value of the mask and jumping to the stage of fetching a new data unit, until the whole data block is fetched. | 03-12-2009 |
20100223444 | METHOD FOR PERFORMING PLURALITY OF BIT OPERATIONS AND A DEVICE HAVING PLURALITY OF BIT OPERATIONS CAPABILITIES - A method and a device having a plurality of bit operations capability, the device includes: a first and a second registers and an instruction fetch circuit, and an arithmetic logic unit adapted to: calculate, during a first clock cycle, a position value representative of a position, within a first information vector, of a first bit of information that has a first value; and to multiply the position value by a multiplication factor to provide a first result and to alter the value of the first bit to a second value to provide an updated information vector, during the first clock cycle. | 09-02-2010 |
20120155570 | DEVICE AND METHOD FOR PERFORMING BITWISE MANIPULATIONS - A device and a method for performing bitwise manipulation is provided. Multiple bitwise logic circuits are coupled to an instruction decoder, a register array and a rotator. Each bitwise logic circuit includes input multiplexers connected to an output multiplexer. The instruction decoder is receives a bit manipulation instruction and sends to each corresponding input multiplexer a control signal based on a type of the instruction. Each input multiplexer of each bitwise logic circuit receives a control signal, a constant signal that has a value that is indifferent to the value of the mask, and a mask affected signal that has a value that is responsive to a value of an associated mask bit. Each input multiplexer selects between the constant signal and the mask affected signal based on the control signal, and outputs a selected signal. Each output multiplexer receives selected signals from each of the corresponding input multiplexers, and elects between the selected signal based on a value of an associated manipulated register bit and based on a value an associated control register bit. | 06-21-2012 |
20120185730 | DISTRIBUTED DEBUG SYSTEM - A distributed debug system including processing elements connected to perform a plurality of processing functions on a received data unit, a debug trap unit, a debug trace dump logic unit, and a debug initiator unit is provided. At least two of the processing elements include a debug trap unit that has a first debug enable input and output, and a first debug thread. The first debug thread holds at least a first debug trap circuit having a match signal output connected to the first debug enable output. The first debug trap circuit filters a part of the data unit, compares a filtering result with a debug value, and provides a match signal to the match signal output. The debug trace dump logic unit dumps debug trace data to a buffer associated with the data unit on reception of a match event. The debug initiator unit includes a debug initiator output connected to the first debug enable input of the debug trap unit of one processing element, and a debug initiator input connected to the first debug enable output of the debug trap unit of another processing element. | 07-19-2012 |
20150234419 | METHODS AND APPARATUS FOR ADAPTIVE TIME KEEPING FOR MULTIPLE TIMERS - A timer distribution module supports multiple timers and comprises: a command decoder arranged to determine expiration times of a plurality of timers; and a timer link list distribution adapter, LLDA, operably coupled to the command decoder. The LLDA is arranged to: receive a time reference from a master clock; receive timer data from the command decoder wherein the timer data comprises at least one timer expiration link list; construct a plurality of timer link lists based on at least one of: the timer expiration link list, at least one configurable timing barrier; dynamically split the link list timer data into a plurality of granularities based on the timer expiration link list; and output the dynamically split link list timer data. | 08-20-2015 |