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Eustis
John Eustis, Saunderstown, RI US
| Patent application number | Description | Published |
|---|---|---|
| 20100107961 | CONVERTIBLE TOP FOR YACHT - A retractable convertible top for a pleasure craft, including a canvas type fabric and stowable linkage mechanism, is described. This convertible top may be fully deployed and retracted automatically to provide a quick and efficient means of providing shelter for the open cabin of a pleasure craft while still allowing easy entrance and egress from the cabin when the top is fully deployed. The convertible top may be fully stowable within a small volume storage bin with watertight covers. The stowage bin may be integrated into the craft. The craft's existing hydraulic and control systems may be utilized to automatically deploy and retract the convertible top. | 05-06-2010 |
Robert H. Eustis, Stanford, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100288130 | APPARATUS FOR AGING WINE OR SPIRITS - A device for the non-deleterious, passive aging of wine wherein the interior of the semi-permeable wall of the aging container, which provides the interface between the wine and the atmosphere, has a substantially larger interface area per unit volume of wine than does that of the prior art device. The device employs a polyhedron shaped aging container or vessel having a volumetric capacity of greater than 30 gallons; and, a relationship (ratio) of the interior surface area of the container to the volume of the container from 0.33 square inches to 1.0 cubic inch to 4.0 square inches to 1.0 cubic inch. In one advantageous embodiment, the container is a rectangular hexahedron. In another advantageous embodiment, the container is a trapezoidal hexahedron. | 11-18-2010 |
Steven M. Eustis, Essex Junction, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20080256405 | COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS - A method of implementing a compilable memory structure configured for supporting multiple test methodologies includes configuring a first plurality of multiplexers for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection, the memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, facilitating observation of the memory logic connection at the customer chip. | 10-16-2008 |
| 20090319818 | METHOD AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE - A method is provided for operating an interface between a first unit and a second unit supplying its data. The method includes switching control between LSSD_B and LSSD_C clocks and system clock (CLK) to provide a test mode of operation and a functional mode of operation to optimize setup and hold times depending on conditions under which the unit is operating. In the test mode, data is launched by the LSSD_C clock. In the functional mode, the data is launched by the system clock (CLK) to RAM. A method is also provided to determine which memory inputs should use a circuit that provides adequate setup and hold margins. | 12-24-2009 |
| 20090319841 | STRUCTURE AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes an input register coupled to a data processing unit input and a test operation mode and functional operation mode. In the test mode operation, the register operates in a clocked mode such that, during the test operation mode, the register propagates data to the data processing unit in response to a clock signal. In the functional operation mode, the register operates in a data flush mode such that the register propagates data to the data processing unit in response to the data. The functional mode is enabled by a flush enable signal and the test mode is enabled by an opposite state of the flush enable signal. | 12-24-2009 |
Susan Eustis US
| Patent application number | Description | Published |
|---|---|---|
| 20110119344 | Apparatus And Method For Using Distributed Servers As Mainframe Class Computers - The invention consists of a switch or bank of switches that give hundreds or thousands of servers the ability to share memory efficiently. It supports improving distributed server utilization from 10% on average to 100%. The invention consists of connecting distributed servers via a cross point switch to a back plane shared random access (RAM) memory thereby achieving a mainframe class computer. The distributed servers may be Windows PCs or Linux standalone computers. They may be clustered or virtualized. This use of cross point switches provides shared memory across servers, improving performance. | 05-19-2011 |