| Patent application number | Description | Published |
|---|
| 20090191687 | METHOD OF FILLING A TRENCH AND METHOD OF FORMING AN ISOLATING LAYER STRUCTURE USING THE SAME - A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are then implanted into a portion of the preliminary insulating layer adjacent the top of the first trench to form a first insulating layer having a doped region and an undoped region. The doped region is removed to form a first insulating layer pattern at the bottom and sides of the first trench, and which first insulating layer pattern defines a second trench. The second trench is then filled with insulating material. | 07-30-2009 |
| 20100240194 | Method of fabricating semiconductor device - A method of fabricating a semiconductor device, the method including sequentially forming a pad oxide layer and a nitride layer on a substrate; etching the nitride layer, the pad oxide layer, and the substrate to form a trench; forming a sidewall oxide layer on a sidewall and a bottom of the trench; forming a oxide layer liner including nitrogen on the sidewall oxide layer; and forming a gap fill layer on the oxide layer liner | 09-23-2010 |
| 20100248471 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided is a method for fabricating a semiconductor device, including forming an interconnect structure including first and second interconnects and an insulating material between the first and second interconnects, forming a first mask layer and a second mask layer having a plurality of micropores sequentially on the interconnect structure, coalescing the plurality of micropores in the second mask layer with each other and forming a plurality of first microholes in the second mask layer, forming a plurality of second microholes in the first mask layer using the plurality of first microholes, and removing the insulating material using the first mask layer with the plurality of second microholes as an etch mask so as to form an air-gap between the first and second interconnects. | 09-30-2010 |
| 20110039393 | METHOD OF FABRICATING A SEMICONDUCTOR MICROSTRUCTURE - Provided is a method of fabricating a semiconductor microstructure, the method including forming a lower material layer on a semiconductor substrate, the lower material layer including a nitride of a Group III-element; forming a mold material layer on the lower material layer; forming an etching mask on the mold material layer, the etching mask being for forming a structure in the mold material layer; anisotropic-etching the mold material layer and the lower material layer by using the etching mask; and isotropic-etching the mold material layer and the lower material layer. | 02-17-2011 |
| 20110241184 | INTEGRATED CIRCUIT DEVICES HAVING SELECTIVELY STRENGTHENED COMPOSITE INTERLAYER INSULATION LAYERS AND METHODS OF FABRICATING THE SAME - An integrated circuit device includes a plurality of stacked circuit layers, at least one of the plurality of circuit layers including a composite interlayer insulation layer including laterally adjacent first and second insulating material regions having different mechanical strengths and dielectric properties and a plurality of circuit components disposed in the composite interlayer insulation layer. The first insulating material region may have a lower dielectric constant and a lower mechanical strength than the second insulating material region such that, for example, the first insulating material region may be positioned near signal lines or other circuit features to reduce capacitance while using the second insulating material region near a location that is susceptible to localized mechanical stress, such as a fuse location, an external connection bonding location or a scribe line location. | 10-06-2011 |
| 20110256708 | Methods of Manufacturing Flash Memory Devices by Selective Removal of Nitrogen Atoms - A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer. | 10-20-2011 |
| 20110281427 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Example embodiments herein relate to a method of fabricating a semiconductor device. The method may include forming a liner insulating layer on a surface of a gate pattern to have a first thickness. Subsequently, a gap fill layer may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness, which is smaller than the first thickness, in the region in which a metal silicide will be formed. Metal silicide may be formed on the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer. | 11-17-2011 |
| 20110306195 | METHOD OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES - In a vertical semiconductor device and a method of manufacturing a vertical semiconductor device, sacrificial layers and insulating interlayers are repeatedly and alternately stacked on a substrate. The sacrificial layers include boron (B) and nitrogen (N) and have an etching selectivity with respect to the insulating interlayers. Semiconductor patterns are formed on the substrate through the sacrificial layers and the insulating interlayers. The sacrificial layers and the insulating interlayers are at least partially removed between the semiconductor patterns to form sacrificial layer patterns and insulating interlayer patterns on sidewalls of the semiconductor patterns. The sacrificial layer patterns are removed to form grooves between the insulating interlayer patterns. The grooves expose portions of the sidewalls of the semiconductor patterns. A gate structure is formed in each of the grooves. | 12-15-2011 |
