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Eunkee Hong
Eunkee Hong, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090191687 | METHOD OF FILLING A TRENCH AND METHOD OF FORMING AN ISOLATING LAYER STRUCTURE USING THE SAME - A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are then implanted into a portion of the preliminary insulating layer adjacent the top of the first trench to form a first insulating layer having a doped region and an undoped region. The doped region is removed to form a first insulating layer pattern at the bottom and sides of the first trench, and which first insulating layer pattern defines a second trench. The second trench is then filled with insulating material. | 07-30-2009 |
| 20100240194 | Method of fabricating semiconductor device - A method of fabricating a semiconductor device, the method including sequentially forming a pad oxide layer and a nitride layer on a substrate; etching the nitride layer, the pad oxide layer, and the substrate to form a trench; forming a sidewall oxide layer on a sidewall and a bottom of the trench; forming a oxide layer liner including nitrogen on the sidewall oxide layer; and forming a gap fill layer on the oxide layer liner | 09-23-2010 |
| 20100248471 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided is a method for fabricating a semiconductor device, including forming an interconnect structure including first and second interconnects and an insulating material between the first and second interconnects, forming a first mask layer and a second mask layer having a plurality of micropores sequentially on the interconnect structure, coalescing the plurality of micropores in the second mask layer with each other and forming a plurality of first microholes in the second mask layer, forming a plurality of second microholes in the first mask layer using the plurality of first microholes, and removing the insulating material using the first mask layer with the plurality of second microholes as an etch mask so as to form an air-gap between the first and second interconnects. | 09-30-2010 |
| 20110039393 | METHOD OF FABRICATING A SEMICONDUCTOR MICROSTRUCTURE - Provided is a method of fabricating a semiconductor microstructure, the method including forming a lower material layer on a semiconductor substrate, the lower material layer including a nitride of a Group III-element; forming a mold material layer on the lower material layer; forming an etching mask on the mold material layer, the etching mask being for forming a structure in the mold material layer; anisotropic-etching the mold material layer and the lower material layer by using the etching mask; and isotropic-etching the mold material layer and the lower material layer. | 02-17-2011 |
Eunkee Hong, Sungnam-Shi KR
| Patent application number | Description | Published |
|---|---|---|
| 20100203700 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes preparing a substrate having a recessed area. A silicon oxide layer is formed at the recessed area. A catalytic nitridation treatment is performed for an upper portion of the silicon oxide layer to form a nitridation reactant on the upper portion of the silicon oxide layer. A dielectric layer is formed on the silicon oxide layer where the nitridation reactant is formed. The dielectric layer is annealed. According to the foregoing method, recession of the dielectric layer is prevented to fabricate a high-quality semiconductor device. | 08-12-2010 |
| 20100230741 | SEMICONDUCTOR DEVICES WITH AN AIR GAP IN TRENCH ISOLATION DIELECTRIC - A tunnel insulating layer and a charge storage layer are sequentially stacked on a substrate. A recess region penetrates the charge storage layer, the tunnel insulating layer and a portion of the substrate. The recess region is defined by a bottom surface and a side surface extending from the bottom surface. A first dielectric pattern includes a bottom portion covering the bottom surface and inner walls extending from the bottom portion and covering a portion of the side surface of the recess region. A second dielectric pattern is in the recess region between the inner walls of the first dielectric pattern, and the second dielectric pattern enclosing an air gap. The air gap that is enclosed by the second dielectric pattern may extend through a major portion of the second dielectric pattern in a direction away from the bottom surface of the recess region. | 09-16-2010 |
| 20110127600 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating thereof, including preparing a substrate including a first and second region; forming first and second conductive lines on the first and second region, respectively, the first conductive lines being spaced apart at a first interval and the second conductive lines being spaced apart at a second interval wider than the first interval; forming a dielectric layer in spaces between the first and second conductive lines; etching the dielectric layer until a top surface thereof is lower than top surfaces of the first conductive lines and the second conductive lines; forming a spacer on the etched dielectric layer such that the spacer covers an entire top surface of the etched dielectric layer between the first conductive lines and exposes portions of the etched dielectric layer between the second conductive lines; and removing portions of the etched dielectric layer between the second conductive lines. | 06-02-2011 |
Eunkee Hong, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090012221 | COMPOSITIONS INCLUDING PERHYDRO-POLYSILAZANE USED IN A SEMICONDUCTOR MANUFACTURING PROCESS - A film is formed on a substrate including conductive patterns or trenches using a composition that included a solvent and perhydro-polysilazane having a weight average molecular weight of about 1,800 to 3,000 and a molecular weight distribution of more than about 2.2 to about 3.0. The film is changed into a silicon oxide film, and then an opening is formed through the silicon oxide film. A contact is formed in the opening by filling the opening with conductive material. The silicon oxide film of perhydro-polysilazane having low molecular weight becomes dense and uniform. | 01-08-2009 |
| 20100167490 | Method of Fabricating Flash Memory Device - Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed. | 07-01-2010 |