Patent application number | Description | Published |
20100072593 | Semiconductor package and method for manufacturing the same - A semiconductor package includes a first package including at least one first semiconductor chip; a second package including an external connection terminal and at least one second semiconductor chip, the second package being stacked on the first package; and an interposer disposed between the first and second packages and connected to the external connection terminal to electrically connect the first and second packages to each other. The interposer comprises an intermediate connector having an exposed end portion to which the second package is electrically connected via the external connection terminal and a protruding end portion lower than the exposed end portion to which the first package is electrically connected. | 03-25-2010 |
20100096754 | Semiconductor package, semiconductor module, and method for fabricating the semiconductor package - Provided is a semiconductor package, a semiconductor module and a method for fabricating the semiconductor package. The method provides a substrate including a bonding pad. The method forms a dielectric layer for exposing the bonding pad on the substrate. The method forms a redistribution line which is electrically connected to the bonding pad, on the dielectric layer. The method forms an external terminal which is electrically connected to the bonding pad without using a solder mask which limits a position of the external terminal, on the redistribution line. | 04-22-2010 |
20100190333 | METHOD OF FORMING CONNECTION TERMINAL - A method of forming a connection terminal may include preparing a substrate, forming a first conductor of a tube shape having an opened upper portion on the substrate, forming a second conductor on the first conductor, and annealing the second conductor so that a portion of the second conductor extends in an internal space of the first conductor through the opened upper portion. | 07-29-2010 |
20110186220 | APPARATUS FOR MANUFACTURING BONDING STRUCTURE, BONDING STRUCTURE AND METHOD OF FABRICATING THE SAME - Provided is an apparatus for manufacturing a bonding structure, a bonding structure, and a method of fabricating the same. The bonding structure includes a pad including an upper surface with a first area, a ball adhered to the upper surface of the pad, and a wire extending from the ball. An adhesion surface of the ball adhered to the pad may have substantially the same shape as that of the upper surface of the pad. | 08-04-2011 |
20110215444 | PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES HAVING THE SAME, AND METHODS OF FABRICATING THE SEMICONDUCTOR PACKAGES - A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip. | 09-08-2011 |
20120001329 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method for fabricating the same. The semiconductor package includes a first substrate including a first pad, a second substrate spaced apart from the first substrate and where a second pad is formed to face the first pad, a first bump electrically connecting the first pad to the second pad, and a second bump mechanically connecting the first substrate to the second substrate is disposed between the first substrate where the first pad is not formed and the second substrate where the second pad is not formed. A coefficient of thermal expansion (CTE) of the second bump is smaller than that of the first bump. | 01-05-2012 |
20120031953 | APPARATUS FOR BUMP REFLOW AND METHODS OF FORMING BUMPS USING THE SAME - A method of forming wafer level bump includes forming at least one pre-bump on a first surface of a wafer, and performing a bump reflow process to the pre-bump while the first surface faces downward, such that a bump is formed. | 02-09-2012 |
20120091579 | Semiconductor Packages And Methods Of Fabricating The Same - A semiconductor package includes a wiring board including an upper connection pad provided on a first surface and a lower connection pad provided on a second surface opposite to the first surface, a semiconductor chip having a bonding pad area in which a bonding pad is provided and an adhesive area except the bonding pad area, and being mounted on the first surface of the wiring board in a flip-chip manner such that the bonding pad is electrically connected to the upper connection pad, a first molding layer provided between the adhesive area of the semiconductor chip and the first surface of the wiring board, and a second molding layer provided between the bonding pad area of the semiconductor chip and the first area of the wiring board while covering the first surface of the wiring board and the semiconductor chip. The first molding layer has a lower modulus than the second molding layer. | 04-19-2012 |
20130178016 | METHODS OF FABRICATING A PACKAGE-ON-PACKAGE DEVICE AND PACKAGE-ON-PACKAGE DEVICES FABRICATED BY THE SAME - Methods of fabricating a package-on-package device and package-on-package devices fabricated by the same may be provided. According to inventive concepts, a back-grinding of a semiconductor chip to a target thickness may be performed after the semiconductor chip is molded by a molding layer. Accordingly, the semiconductor chip is relatively thick while forming a molding layer, and thus less susceptible to a warpage phenomenon, which for instance may occur during the forming a molding layer. Thus, relatively thin package-on-package device, which is less susceptible to the warpage phenomenon, may be achieved. | 07-11-2013 |
20130288431 | PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES HAVING THE SAME, AND METHODS OF FABRICATING THE SEMICONDUCTOR PACKAGES - A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip. | 10-31-2013 |
20140151863 | SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME - A semiconductor package includes a wiring board, a semiconductor chip mounted on the wiring board, and a mounting connection terminal electrically connecting a bonding pad of the semiconductor chip to a first connection pad of the wiring board. The mounting connection terminal includes a core portion and a connecting shell solder portion substantially surrounding the core portion. The core portion of the mounting connection terminal is not in contact with the bonding pad of the semiconductor chip. | 06-05-2014 |
20140374883 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package, comprising: a semiconductor substrate; a mold layer on the semiconductor substrate; and a marking formed on a surface of the mold layer, the marking comprising dot markings substantially discontinuously arranged in vertical and horizontal directions of a display region. An effective area of the dot markings within a unit display region of the marking is smaller than about half a total area of the unit display region. | 12-25-2014 |