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Eun-Suk
Eun-Suk Cho, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20080303079 | Non-volatile Memory Cells Including Fin Structures - A method of forming a non-volatile memory device may include forming a fin protruding from a substrate, forming a tunnel insulating layer on portions of the fin, and forming a floating gate on the tunnel insulting layer so that the tunnel insulating layer is between the floating gate and the fin. A dielectric layer may be formed on the floating gate so that the floating gate is between the dielectric layer and the fin, and a control gate electrode may be formed on the dielectric layer so that the dielectric layer is between the control gate and the fin. Related devices are also discussed. | 12-11-2008 |
| 20080315282 | Semiconductor Devices Including Transistors Having Three Dimensional Channels - Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the semiconductor fin. A channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode is also provided. Doped region is provided in the semiconductor fin at either side of the gate electrode and an interlayer insulating layer is provided on a surface of the semiconductor substrate. A connector region is coupled to the doped region and provided in an opening, which penetrates the interlayer insulating layer. A recess region is provided in the doped region and is coupled to the connector region. The connector region contacts an inner surface of the recess region. Related methods of fabricating semiconductor devices are also provided herein. | 12-25-2008 |
Eun-Suk Cho, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080293215 | Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions - Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed. | 11-27-2008 |
Eun-Suk Jung, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100184491 | PHONE - A phone is provided. The phone comprises a first body having a first face, a second body having a second face facing the first face and connected to the first body so as to be slidable in a moving direction parallel to the first and second faces, guiding members protruding from the first face, and a sliding member mounted on the second face and guiding the guiding members so as to slide in the moving direction. The sliding member includes insert members, each of which has a guide groove, disposed parallel to the moving direction to allow the respective guiding members to be inserted thereinto and housings fixedly mounted on the second face to house the respective insert members. The space defined by the first body and the second body is minimized. With this configuration, the first body is movable in a circular arc direction relative to the second body and has the same curvature as the second body. | 07-22-2010 |
Eun-Suk Kim, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090253337 | APPARATUS AND METHOD FOR BAKING FLUORESCENT LAMP - This disclosure relates to an apparatus and a method for making or baking a fluorescent lamp. An apparatus for baking a fluorescent lamp includes a heater to heat a plurality of quartz tubes. Each tube has a fluorescent lamp provided therein. A plurality of rollers rotates the quartz tubes placed thereon, and a transfer block has a plurality of auxiliary rollers. The transfer block is configured to move in a first direction to transfer the plurality of quartz tubes from the plurality of rotating rollers to the plurality of auxiliary rollers. A process for heating at least one fluorescent lamp includes a step of providing a plurality of quartz tubes on a plurality of rotating rollers, at least one quartz tube having a fluorescent lamp provided therein, heating the plurality of quartz tubes while being rotated on the plurality of rollers, and transferring the plurality of quartz tube using a transfer block having a plurality of auxiliary rollers. | 10-08-2009 |
Eun-Suk Seo, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20090125029 | Device for Aligning and Guiding Femoral Resection Guide and Femoral Implant Impactor - The present invention discloses a device for aligning and guiding a femoral resection guide and a femoral implant impactor, whereby the femoral resection guide and the femoral implant impactor are aligned perpendicular to the mechanical axes of the coronal plane and sagittal plane of the femur at the bottom end of the femur, and are guided so as to be rotation-aligned and mounted in parallel with a condyle axis connecting the inner condyle and outer condyle. The device comprises a main frame | 05-14-2009 |