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Eun Soo
Eun Soo Cha, Gwacheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080238300 | Organic electroluminescence device and method for fabricating the same - Disclosed herein are an organic electroluminescent (EL) device comprising a hole transport layer (HTL) and a method for fabricating the same. The organic electroluminescent (EL) device comprises a stack in which a light-emitting layer and a hole transport layer are interposed between an anode and a cathode, wherein the hole transport layer is made of a mixture of at least two materials, and wherein the mixture is selected from a mixture of an organic compound and one or more other organic compounds, a mixture of a metal or inorganic compound and one or more other metal or inorganic compounds, and a mixture of one or more organic compounds and one or more metal or inorganic compounds. | 10-02-2008 |
Eun Soo Choi, Daejeon KR
| Patent application number | Description | Published |
|---|---|---|
| 20110275786 | PROCESS FOR PURIFYING VANCOMYCIN WET BODY - Provided is a process for purifying a vancomycin wet body, comprising: dissolving a wet body obtained from a microorganism-fermented solution containing vancomycin into a water soluble solvent to a concentration of about 1 to 40 g/L and carrying out reverse osmosis filtration; and carrying out lyophilization of the filtered vancomycin. The process for purifying a vancomycin wet body provides high-purity vancomycin, while avoiding degradation of stability during a drying step. | 11-10-2011 |
Eun Soo Choi, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20090165404 | METHOD FOR RETROFITTING REINFORCED CONCRETE COLUMN USING MULTI-LAYERED STEEL PLATES, AND RETROFITTING STRUCTURE OF REINFORCED CONCRETE COLUMN USING THE SAME - A method for retrofitting a reinforced concrete column by compressing a reinforcing plate including a steel plate using an external pressure is provided. The reinforcing plate is compressed to double-layer or more, that is, multi-layer in due order, on the reinforced concrete column. Accordingly, since a workability of the retrofit is excellent and since the reinforcing plate is easily compressed on the surface of the reinforced concrete column by a small lateral pressure, sufficiently the reinforced concrete column could be reinforced. Besides, a compressive strength of the reinforced concrete column could be increased. In addition, the flexibility of the reinforcing plate and the energy absorption force of the reinforcing plate could be increased. | 07-02-2009 |
Eun Soo Hwang, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100243021 | Solar cells and methods for manufacturing the same - Solar cells and methods of manufacturing the same are provided, the solar cell include a plurality of unit cells connected to one another on the same level of a substrate to form a module, each of the unit cells including a first electrode and a second electrode having opposite polarities and an active layer interposed between the first electrode and the second electrode. | 09-30-2010 |
Eun Soo Jeong, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20080286973 | METHOD FOR FORMING SEMICONDUCTOR FINE-PITCH PATTERN - A method for forming a fine-pitch pattern on a semiconductor substrate is provided. The method includes patterning the semiconductor substrate to form a plurality of fine lines, forming a thermal oxide layer on the fine lines, polishing the thermal oxide layer to expose a top surface of the fine lines; etching the fine lines using the thermal oxide layer as a mask to expose first portions of the semiconductor substrate, etching a central bottom portion of the thermal oxide layer to expose second portions of the semiconductor substrate, and etching the semiconductor substrate using the etched thermal oxide layer as a mask. | 11-20-2008 |
Eun Soo Lee, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100156833 | ELECTRONIC DEVICE HAVING TOUCH SCREEN AND METHOD FOR CHANGING DATA DISPLAYED ON THE TOUCH SCREEN - In a time data display mode, a time data is displayed in at least one display block partially assigned to a touch screen of an electronic device. After the touch gesture or the drag gesture is detected in one of the display block, the current time data in the display block can be replaced with a new time data according to the touch gesture or the drag gesture. The new time data may be a following time data or a previous time data which can be determined according to a location of the touch gesture, or a direction and a distance of the drag gesture. In addition, the extent of a change in the time data may be determined according to duration of the touch gesture or a speed of the drag gesture. | 06-24-2010 |
Eun Soo Nam, Daejeon-City KR
| Patent application number | Description | Published |
|---|---|---|
| 20090140291 | PHOTO-DETECTOR FOR DETECTING IMAGE SIGNAL OF INFRARED LASER RADAR AND METHOD OF MANUFACTURING THE SAME - A photo-detector, in which metal wiring for connecting electrodes is arranged on a planarized surface and thus the metal wiring arrangement is simplified, and a method of manufacturing the same are provided. The photo-detector includes a multi-layer compound semiconductor layer formed on a compound semiconductor substrate. A number of p-n junction diodes are arranged in a regular order in a selected region of the compound semiconductor layer, and an isolation region for individually isolating the p-n junction diodes is formed by implanting impurity ions in the multi-layer compound semiconductor layer. The isolation region and the surface of the compound semiconductor layer are positioned on the same level. The isolation region may be a Fe-impurity region. | 06-04-2009 |
| 20090239328 | PHOTO-DETECTOR FOR DETECTING IMAGE SIGNAL OF INFRARED LASER RADAR AND METHOD OF MANUFACTURING THE SAME - A photo-detector, in which metal wiring for connecting electrodes is arranged on a planarized surface and thus the metal wiring arrangement is simplified, and a method of manufacturing the same are provided. The photo-detector includes a multi-layer compound semiconductor layer formed on a compound semiconductor substrate. A number of p-n junction diodes are arranged in a regular order in a selected region of the compound semiconductor layer, and an isolation region for individually isolating the p-n junction diodes is formed by implanting impurity ions in the multi-layer compound semiconductor layer. The isolation region and the surface of the compound semiconductor layer are positioned on the same level. The isolation region may be a Fe-impurity region. | 09-24-2009 |
Eun Soo Nam, Soo KR
| Patent application number | Description | Published |
|---|---|---|
| 20110096855 | POLARIZATION DIVISION MULTIPLEXED OPTICAL ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING TRANSMITTER AND RECEIVER - Provided is a polarization division multiplexed optical OFDM transmitter. The polarization division multiplexed optical OFDM transmitter includes a data demultiplexer, a training symbol generation unit and an optical up-converter and polarization division multiplexing unit. The data demultiplexer divides a transmission signal into a plurality of groups. The training symbol generation unit allocates a plurality of training symbols for each OFDM data which is included in the respective multiplexed groups, and allocates repetitive data in a time domain for the respective training symbols for data of 0 to periodically appear for the respective training symbols in a frequency domain. The optical up-converter and polarization division multiplexing unit performs optical frequency band conversion and polarization division multiplexing on an output of the training symbol generation unit to output a polarization division multiplexed optical OFDM signal corresponding to a plurality of polarization components. | 04-28-2011 |
Eun Soo Park, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090260720 | Nd-based two-phase separation amorphous alloy - Provided is a Nd-based two-phase separation amorphous alloy by adding an element having a big difference in heat of mixing in a Nd-based alloy with a superior amorphous formability through an inherent characteristic of compositional elements and consideration of thermodynamics, at the time of forming amorphous phase, to thereby enable two-phase separation amorphous alloy during solidification. The Nd-based two-phase separation amorphous alloy is represented as a general equation Nd | 10-22-2009 |
Eun-Soo Jeong, Eumseong-Gun KR
| Patent application number | Description | Published |
|---|---|---|
| 20090146229 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Embodiments relate to a semiconductor device and a method for fabricating the same. According to embodiments, a semiconductor device may include a metal film spaced from a semiconductor substrate at a predetermined interval and in which a plurality of etching holes are formed. A bottom metal pattern disposed on and/or over a space between the semiconductor substrate and metal film and top metal pattern formed on and/or over the bottom metal pattern may be provided. A pillar may be formed on and/or over the semiconductor substrate and may support one side of a low surface of the bottom metal pattern. A pad may be formed on and/or over the semiconductor substrate, and an air layer corresponding to the bottom metal pattern may be inserted therein. According to embodiments, a pyro-electric switch transistor using a bi-metal with different coefficients of thermal expansion may be provided. | 06-11-2009 |
Eun-Soo Jeong, Gangnam-Gu KR
| Patent application number | Description | Published |
|---|---|---|
| 20080305637 | METHOD FOR FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE - A method for forming a fine pattern of a semiconductor device which includes sequentially forming a non-etching layer and a sacrificial layer on a semiconductor substrate; and then forming a plurality of photo-resist layer patterns having a plurality of openings exposing the sacrificial layer; and then forming a plurality of first pattern grooves in the sacrificial layer etching the exposed sacrificial layer using the photo-resist patterns as an etching barrier; removing the photo-resist layer; and then forming an oxidation layer having a plurality of second pattern grooves on the sacrificial layer and in the first pattern grooves by performing a thermal oxidation process on the sacrificial layer; and then forming a plurality of first through-holes exposing the non-etching layer by completely removing the sacrificial layer remaining in oxidation layer; and then forming a plurality of patterns in the non-etching layer by etching the exposed portions of the non-etching layer using the oxidation layer as an etching barrier. | 12-11-2008 |
| 20090021710 | IMMERSION LITHOGRAPHY APPARATUS AND METHOD OF FORMING PATTERN USING THE SAME - An immersion lithography apparatus and/or a method of forming a pattern. In an immersion lithography apparatus, an intermediate medium may not directly contact the photoresist layer and it may be possible to maximize the transport speed of a wafer without generating defects (e.g. water marks). An intermediate medium may include a first intermediate medium and a second intermediate medium that for an interface. The interface may be controlled by charges through an electrode to control a numerical aperture. Accordingly, a pattern may be formed using an immersion lithography apparatus capable of controlling a numerical aperture so that a relatively high refractive index can be achieved. | 01-22-2009 |
| 20100060104 | PIEZOELECTRIC TRANSISTOR AND METHOD OF MANUFACTURING SAME - A piezoelectric transistor including a substrate, such as a semiconductor substrate. The substrate may include a cavity and the cavity may be etched downward. A piezoelectric transistor may include piezoelectric material formed over the semiconductor substrate in a cantilever form, and may be elastically strained up and/or down. A piezoelectric transistor may include metal material electrically connected to the piezoelectric material by the piezoelectric effect, and metal wiring may supply voltage to piezoelectric material. Methods of fabricating the same are disclosed. | 03-11-2010 |
Eun-Soo Jeong, Eumsaong-Gun KR
| Patent application number | Description | Published |
|---|---|---|
| 20090160064 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE DEVICE - A semiconductor device and a method for manufacturing the device that minimizes a line width while maximizing integration density of the semiconductor device. The method includes forming an interlayer insulating film on a semiconductor substrate, and then forming a first via hole in the interlayer insulating film, and then forming a resin material in the first via hole, and then forming a plurality of second via holes in the interlayer insulating film laterally, and then forming a resin material in the second via holes, and then simultaneously forming a plurality of third via holes in the interlayer insulating film and a trench spatially above and corresponding to the first via hole, and then removing the resin formed in the first via hole and the second via holes, and then simultaneously forming metal layers in the first via hole and the second and third via holes and the trench. | 06-25-2009 |
Eun-Soo Kim, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080251697 | IMAGE SENSOR AND METHOD OF FABRICATION - Disclosed is an image sensor and method of fabricating the same. The image sensor includes a photoelectric transformation region formed in a semiconductor substrate, and pluralities of interlayer dielectric films formed over the photoelectric transformation regions. The interlayer dielectric films contain multilevel interconnection layers. A color filter layer is disposed in a well region formed in the interlayer dielectric films over the photoelectric transformation region. A passivation layer is interposed between the color filter layer and the interlayer dielectric films. | 10-16-2008 |
| 20110204468 | Image sensor and method of manufacturing the same - Example embodiments disclose an image sensor capable of preventing or reducing image lag and a method of manufacturing the same. Example methods may include forming a gate insulating film and a gate conductive film doped with a first-conductive-type dopant on a semiconductor substrate; forming a transfer gate pattern by patterning the gate insulating film and the gate conductive film; and fabricating a transfer gate electrode by forming a first-conductive-type photodiode in the semiconductor substrate adjacent to one region of the transfer gate pattern, by forming a second-conductive-type photodiode on the first-conductive-type photodiode, and by forming a first-conductive-type floating diffusion region in the semiconductor substrate adjacent to the other region of the transfer gate pattern. | 08-25-2011 |
Eun-Soo Kim, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20080211737 | Three-dimensional display apparatus using intermediate elemental images - A three-dimensional image display apparatus using an intermediate elemental image is disclosed. In one embodiment, the three-dimensional image display apparatus includes: i) an image input unit, generating a plurality of elemental images extracted from a three-dimensional object, the elemental images have different perspectives, ii) an image processing unit, generating an intermediate elemental image, using parallax information between the elemental images inputted from the image input unit and iii) an image reproduction unit, reproducing a three-dimensional image corresponding to the three-dimensional object, using the elemental image and the intermediate elemental image. With the three-dimensional image display apparatus, and the method thereof, using an intermediate elemental image in accordance with at least one embodiment of the present invention, a high-resolution three-dimensional image can be outputted. | 09-04-2008 |
| 20080291269 | 3D IMAGE DISPLAY METHOD AND SYSTEM THEREOF - A three-dimensional image display method is disclosed. The three-dimensional image display method in accordance with an embodiment of the present invention includes: displaying an object image; displaying a background image by using a three-dimensional image display method; and disposing the object image at a close distance and the background image at a far distance such that the object image and the background image overlap inside a same viewing angle. By using images having a different sense of depth, a high-resolution image can be displayed while providing a sense of reality. | 11-27-2008 |
| 20090033741 | 2D-3D CONVERTIBLE DISPLAY DEVICE AND METHOD HAVING A BACKGROUND OF FULL-PARALLAX INTEGRAL IMAGES - A two dimensional to three dimensional (2D-3D) convertible display device is disclosed. In one embodiment, the display device includes i) a first display unit configured to selectively output one of a composite image and backlight, wherein the composite image comprises a background image and a mask image, for an object, wherein the background image comprises element images for a background excluding the object and wherein the mask image is a white image which has the same shape as that of the object, ii) a lens unit configured to convert the composite image into a stereoscopic image or pass through the backlight and iii) a second display unit configured to output i) a two-dimensional (2D) image of the object by the use of the backlight at a 2D mode and ii) the combination of the 2D image and the composite image at a three dimensional (3D) mode. | 02-05-2009 |
Eun-Soo Nam, Daejeon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100133586 | HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF FORMING THE SAME - Provided are a heterojunction bipolar transistor and a method of forming the same. The method includes forming an emitter electrode on an emitter capping pattern, a base electrode on a base pattern, and a collector electrode on a subcollector pattern, the subcollector pattern, the base pattern, an emitter pattern, and the emitter capping pattern being provided to a substrate; patterning a protection insulation layer and a first dummy pattern covering the emitter electrode, the base electrode, and the collector electrode, to expose the emitter electrode, the base electrode, and the collector electrode; forming a second dummy pattern to electrically separate the emitter electrode, the base electrode, and the collector electrode; forming, on the substrate provided with the second dummy pattern, an emitter electrode interconnection connected to the emitter electrode, a base electrode interconnection connected to the base electrode, and a collector electrode interconnection connected to the collector electrode; and removing the first and second dummy patterns. | 06-03-2010 |