Patent application number | Description | Published |
20100258852 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed. | 10-14-2010 |
20100314678 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a non-volatile memory device, the method includes alternately stacking inter-layer dielectric layers and sacrificial layers over a substrate, etching the inter-layer dielectric layers and the sacrificial layers to form trenches to expose a surface of the substrate, etching the inter-layer dielectric layers exposed by the trenches to a predetermined thickness, forming junction layers over etched portions of the inter-layer dielectric layers, and burying a layer for a channel within the trenches in which the junction layers have been formed to form a channel. | 12-16-2010 |
20100327323 | THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A three-dimensional nonvolatile memory device includes: a plurality of channel structures extending in parallel in a first direction and comprising a plurality of channel layers that are alternatively stacked with a plurality of interlayer insulating layers over a substrate; a plurality of memory cells stacked along sidewalls of the channel structures and arranged in the first direction and a second direction crossing the first direction; and a plurality of word lines extending in parallel in the second direction and connected to the memory cells arranged in the second direction. | 12-30-2010 |
20110090737 | 3D NON-VOLATILE MEMORY DEVICE AND METHOD FOR OPERATING AND FABRICATING THE SAME - A 3D non-volatile memory device includes a plate-type lower select line formed over a substrate, a lower select transistor formed in the lower select line, a plurality of memory cells stacked over the lower select transistor, an upper select transistor formed over the memory cells, and a line-type common source line formed over the substrate and spaced from the lower select line. | 04-21-2011 |
20110169072 | 3D NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A 3D nonvolatile memory device includes a plurality of channel structures each comprising a plurality of channel layers and interlayer dielectric layers which are alternately stacked, a plurality of channel contacts coupled to the plurality of channel layers, respectively, and a plurality of selection lines vertically-coupled to the plurality of channel contacts and crossing over the plurality of channel structures. | 07-14-2011 |
20110199813 | NON-VOLATILE MEMORY DEVICE HAVING 3D STRUCTURE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device having a three-dimensional (3D) structure includes a plurality of line-type horizontal electrode structures configured to include a plurality of interlayer dielectric layers and a plurality of horizontal electrodes that are alternately stacked over a substrate, a plurality of pillar-type vertical electrodes configured to protrude from the substrate while contacting sidewalls of the plurality of the horizontal electrode structures, and a memory layer interposed between the plurality of the horizontal electrode structures and the plurality of the vertical electrodes, and configured to have a resistance value that varies based on a bias applied to the plurality of the horizontal electrodes and the plurality of the vertical electrodes. | 08-18-2011 |
20120168849 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a substrate including a resistor layer having a resistance lower than that of a source line, channel structures including a plurality of inter-layer dielectric layers that are alternately staked with a plurality of channel layers over the substrate, and the source line configured to contact sidewalls of the channel layers, where a lower end of the source line contacts the resistor layer. | 07-05-2012 |
20120211822 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed. | 08-23-2012 |
20120299076 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a channel vertically extending from a substrate and comprising a first region that is doped with first impurities and a second region that is disposed under the first region, a plurality of memory cells and a selection transistor stacked over the substrate along the channel, and a diffusion barrier interposed between the first region and the second region, wherein a density of the first impurities is higher than a density of impurities of the second region. | 11-29-2012 |
20120300547 | 3-DIMENSIONAL NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device comprising a plurality of strings each including a drain select transistor, drain-side memory cells, a pipe transistor, source-side memory cells, and a source select transistor coupled in series, wherein the plurality of strings are arranged in a first direction and a second direction, and the strings arranged in the second direction form each of string columns; a plurality of bit lines extended in the second direction and coupled to the drain select transistors of the strings included in each string column; and a plurality of source lines extended in the first direction and in common coupled to the source select transistors of strings adjacent to each other in the second direction, wherein strings included in one of the string columns are staggered in the first direction and each of the string columns are coupled to at least two of the bit lines. | 11-29-2012 |
20130113033 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device in accordance with one embodiment of the present invention includes a substrate including a P-type impurity-doped region, a channel structure comprising a plurality of interlayer insulating layers that are alternately stacked with a plurality of channel layers on the substrate, a P-type semiconductor pattern that contacts sidewalls of the plurality of channel layers, wherein a lower end of the P-type semiconductor pattern contacts the P-type impurity-doped region, and source lines that are disposed at both sides of the P-type semiconductor pattern and contact the sidewalls of the plurality of channel layers. | 05-09-2013 |
20130128660 | READING METHOD OF NON-VOLATILE MEMORY DEVICE - A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell. | 05-23-2013 |
20130175602 | Non-Volatile Memory Device Having Three Dimensional, Vertical Channel, Alternately Stacked Gate Electrode Structure - A method for fabricating a non-volatile memory device, the method includes alternately stacking inter-layer dielectric layers and sacrificial layers over a substrate, etching the inter-layer dielectric layers and the sacrificial layers to form trenches to expose a surface of the substrate, etching the inter-layer dielectric layers exposed by the trenches to a predetermined thickness, forming junction layers over etched portions of the inter-layer dielectric layers, and burying a layer for a channel within the trenches in which the junction layers have been formed to form a channel. | 07-11-2013 |
20130194869 | THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE - A three-dimensional (3-D) non-volatile memory device according to embodiment of the present invention includes a plurality of bit lines, at least one string row extending in a first direction coupled to the bit lines and including 2N strings, wherein the N includes a natural number, a common source selection line configured to control source selection transistors of the 2N strings included in a memory block, a first common drain selection line configured to control drain selection transistors of a first string and a 2N-th string among the 2N strings included in a memory block, and N−1 second common drain selection lines configured to control drain selection transistors of adjacent strings in the first direction among remaining strings other than the first string and the 2N-th string. | 08-01-2013 |
20140254281 | 3D NON-VOLATILE MEMORY DEVICE AND METHOD FOR OPERATING AND FABRICATING THE SAME - A 3D non-volatile memory device includes a plate-type lower select line formed over a substrate, a lower select transistor formed in the lower select line, a plurality of memory cells stacked over the lower select transistor, an upper select transistor formed over the memory cells, and a line-type common source line formed over the substrate and spaced from the lower select line. | 09-11-2014 |
20140299931 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers. | 10-09-2014 |