| Patent application number | Description | Published |
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| 20080206954 | METHODS OF REDUCING IMPURITY CONCENTRATION IN ISOLATING FILMS IN SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device includes forming a lower device on a lower semiconductor substrate, and forming an interlayer insulating film on the lower device. An upper semiconductor substrate is formed on the interlayer insulating film such that the interlayer insulating film is between the lower and upper semiconductor substrates. Upper trenches are formed within the upper semiconductor substrate. An upper device isolating film is formed within the upper trenches. The upper device isolating film is irradiated with ultraviolet light having a wavelength configured to break chemical bonds of impurities in the upper device isolating film to reduce an impurity concentration thereof. | 08-28-2008 |
| 20100167490 | Method of Fabricating Flash Memory Device - Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed. | 07-01-2010 |
| 20110037109 | SEMICONDUCTOR DEVICES INCLUDING LOWER AND UPPER DEVICE ISOLATION PATTERNS - In some embodiments, a semiconductor substrate includes trenches defining active regions. The semiconductor device further includes lower and upper device isolation patterns disposed in the trenches. An intergate insulation pattern and a control gate electrode are disposed on the semiconductor substrate to cross over the active regions. A charge storage electrode is between the control gate electrode and the active regions. A gate insulation pattern is between the charge storage electrode and the active regions, and the intergate insulation pattern directly contacts the upper device isolation pattern between the active regions. | 02-17-2011 |
| Patent application number | Description | Published |
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| 20090020847 | Semiconductor device having trench isolation region and methods of fabricating the same - A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate. A lower material layer may fill the first and second trench regions. The lower material layer may be etched by a first etching process to form a first preliminary lower material layer pattern remaining in the first trench region and form a second preliminary lower material layer pattern that remains in the second trench region. An upper surface of the second preliminary lower material layer pattern may be at a different height than the first preliminary lower material layer pattern. The first and second preliminary lower material layer patterns may be etched by a second etching process to form first and second lower material layer patterns having top surfaces at substantially the same height. First and second upper material layer patterns may be formed on the first and second lower material layer patterns, respectively. | 01-22-2009 |
| 20090045483 | Semiconductor devices having trench isolation regions and methods of manufacturing semiconductor devices having trench isolation regions - A semiconductor device may include a semiconductor substrate, trench region, buffer pattern, gap fill layer, and transistor. The trench region may be provided in the semiconductor substrate to define an active region. The buffer pattern and gap fill layer may be provided in the trench region. The buffer pattern and gap fill layer may fill the trench region. The gap fill layer may be densified by the buffer pattern. The transistor may be provided in the active region. A method of manufacturing a semiconductor device may include: forming a trench region in a semiconductor substrate; forming a buffer layer on an inner wall of the first trench region; forming a gap fill layer, filling the trench region; performing a thermal process to react the impurity with the oxygen, forming a buffer pattern; and forming a transistor in the active region. | 02-19-2009 |
| 20090191687 | METHOD OF FILLING A TRENCH AND METHOD OF FORMING AN ISOLATING LAYER STRUCTURE USING THE SAME - A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are then implanted into a portion of the preliminary insulating layer adjacent the top of the first trench to form a first insulating layer having a doped region and an undoped region. The doped region is removed to form a first insulating layer pattern at the bottom and sides of the first trench, and which first insulating layer pattern defines a second trench. The second trench is then filled with insulating material. | 07-30-2009 |
| 20100072569 | Method of forming an isolation layer, method of manufacturing a semiconductor device using the same, and semiconductor device having an isolation layer - In a method of forming an isolation layer, a plurality of trenches is formed on a substrate. A liner is formed on inner walls of the trenches. The liner is thermally oxidized to fill up some of the trenches. The other trenches are filled up with an insulation material. As a result, the isolation layer is free of voids. | 03-25-2010 |
| 20110039393 | METHOD OF FABRICATING A SEMICONDUCTOR MICROSTRUCTURE - Provided is a method of fabricating a semiconductor microstructure, the method including forming a lower material layer on a semiconductor substrate, the lower material layer including a nitride of a Group III-element; forming a mold material layer on the lower material layer; forming an etching mask on the mold material layer, the etching mask being for forming a structure in the mold material layer; anisotropic-etching the mold material layer and the lower material layer by using the etching mask; and isotropic-etching the mold material layer and the lower material layer. | 02-17-2011 |
