| Patent application number | Description | Published |
|---|
| 20080212376 | METHODS OF OPERATING AND MANUFACTURING LOGIC DEVICE AND SEMICONDUCTOR DEVICE INCLUDING COMPLEMENTARY NONVOLATILE MEMORY DEVICE, AND READING CIRCUIT FOR THE SAME - Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous. | 09-04-2008 |
| 20090183816 | Method of transferring carbon nanotubes - Provided is a method of transferring carbon nanotubes formed on a donor substrate to an acceptor substrate which may include vertically forming carbon nanotubes on a first substrate, providing a second substrate, aligning the first substrate with the second substrate so that the carbon nanotubes face the second substrate, and transferring the carbon nanotubes onto the second substrate by pressing the first substrate onto the second substrate. | 07-23-2009 |
| 20090186149 | Method of fabricating metal oxide film on carbon nanotube and method of fabricating carbon nanotube transistor using the same - Provided is a method of forming a metal oxide film on a CNT and a method of fabricating a carbon nanotube transistor using the same. The method includes forming chemical functional group on a surface of the CNT and forming the metal oxide film on the CNT on which the chemical functional group is formed. | 07-23-2009 |
| 20090267647 | Convertible logic circuits comprising carbon nanotube transistors having ambipolar charateristics - A convertible logic circuit includes a plurality of carbon nanotube transistors. Each carbon nanotube transistors are configurable as p-type or an n-type transistors according to a voltage of a power source voltage. Each carbon nanotube transistor includes a source electrode, a drain electrode, a channel formed of a carbon nanotube between the source electrode and the drain electrode, a gate insulating layer formed on the carbon nanotubes, and a gate electrode formed on the gate insulating layer. | 10-29-2009 |
| 20100207102 | Static random access memories having carbon nanotube thin films - A static random access memory (SRAM) includes: a first carbon nanotube (CNT) inverter, a second CNT inverter, a first switching transistor, and a second switching transistor. The first CNT inverter includes at least a first CNT transistor. The second CNT inverter is connected to the first CNT inverter and includes at least one second CNT transistor. The first switching transistor is connected to the first CNT inverter. The second switching transistor is connected to the second CNT inverter. | 08-19-2010 |
| 20100291486 | Method of manufacturing carbon nanotube device array - Provided is a method of manufacturing carbon nanotube (CNT) device arrays. In the method of manufacturing CNT device arrays, catalyst patterns may be formed using a photolithography process, CNTs may be grown from the catalyst patterns, and electrodes may be formed on the grown CNTs. | 11-18-2010 |
| 20100296347 | Method of erasing device including complementary nonvolatile memory devices - Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous. | 11-25-2010 |
| 20110095287 | Nonvolatile memory device and nonvolatile memory array including the same - A nonvolatile memory device having self-presence diode characteristics, and/or a nonvolatile memory array including the nonvolatile memory device may be provided. The nonvolatile memory device may include a lower electrode, a first semiconductor oxide layer on the lower electrode, a second semiconductor oxide layer on the first semiconductor oxide layer, and/or an upper electrode on the second semiconductor oxide layer. | 04-28-2011 |
