| Patent application number | Description | Published |
|---|
| 20080258288 | Semiconductor device stack package, electronic apparatus including the same, and method of manufacturing the same - In a semiconductor device stack package and a method of forming the same, the package comprises: a substrate; a plurality of lower chips stacked on the substrate and having an active surface oriented in a direction toward the substrate; and at least one upper chip disposed on the lower chips and connected to the substrate via a bump disposed between the lower chips. As no wire loops are formed, there is no increase in the height of the stack package, and the electrical path is shortened, thereby improving the electric performance of the stack package. Also, the semiconductor device stack package has a flip chip structure, and thus a plurality of semiconductor chips can be stacked in various manners. | 10-23-2008 |
| 20080265432 | MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE MULTI-CHIP PACKAGE - A multi-chip package includes a mounting substrate, a first semiconductor chip, a second semiconductor chip, a reinforcing member, conductive wires and an encapsulant. The first semiconductor chip is disposed on the mounting substrate. The second semiconductor chip is disposed on the first semiconductor chip. An end portion of the second semiconductor chip protrudes from a side portion of the first semiconductor chip. A reinforcing member is disposed on an overlapping region of the second semiconductor chip where the second semiconductor chip overlaps with the side portion of the first semiconductor chip such that the reinforcing member decreases downward bending of the second semiconductor chip from the side portion of the first semiconductor chip. The conductive wires electrically connect the first and second semiconductor chips to the mounting substrate. The encapsulant is disposed on the mounting substrate to cover the first and second semiconductor chips and the conductive wires. | 10-30-2008 |
| 20080268579 | SEMICONDUCTOR CHIP PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor chip package capable of improving reliability at a chip interconnection portion and improving reliability in a solder joint by reducing thermal and mechanical stresses at an external portion of the package including a solder ball land, and a method of fabricating the package are provided. The method of fabricating a semiconductor chip package includes providing a substrate; forming a first underfill on a first portion of the substrate; forming a second underfill at a chip interconnection portion of the substrate; and mounting a semiconductor chip on the chip interconnection portion using conductive bumps. In the method, the second underfill is formed of a material having a modulus higher than the first underfill. | 10-30-2008 |
| 20080283996 | SEMICONDUCTOR PACKAGE USING CHIP-EMBEDDED INTERPOSER SUBSTRATE - A semiconductor package using a chip-embedded interposer substrate is provided. The chip-embedded interposer substrate includes a chip including a plurality of chip pads; a substrate having the chip mounted thereon and including a plurality of redistribution pads for redistributing the chip pads; bonding wires for connecting the chip pads to the redistribution pads; a protective layer having via holes for exposing the redistribution pads while burying the chip and the substrate; and vias connected to the redistribution pads through the via holes. The semiconductor package including chips of various sizes is fabricated using the chip-embedded interposer substrate. | 11-20-2008 |
| 20080284017 | METHODS OF FABRICATING CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE, AND CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE FABRICATED USING THE METHODS - Provided are methods of fabricating a circuit board and a semiconductor package, and a circuit board and a semiconductor package fabricated using the methods. The circuit board comprises: a lower wiring pattern disposed on an upper surface of a resin substrate comprising a filler; a resin layer disposed on the lower wiring pattern; an upper wiring pattern comprising a bonding pad disposed on the resin layer; and a passivation layer comprising an upper opening exposing the bonding pad. The resin substrate comprises a substrate opening exposing a lower surface of the lower wiring pattern. | 11-20-2008 |
| 20080308935 | SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP PACKAGE, AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE - Provided are a semiconductor chip package, a semiconductor package, and a method of fabricating the same. In some embodiments, the semiconductor chip packages includes a semiconductor chip including an active surface, a rear surface, and side surfaces, bump solder balls provided on bonding pads formed on the active surface, and a molding layer provided to cover the active surface and expose portions of the bump solder balls. The molding layer between adjacent bump solder balls may have a meniscus concave surface, where a height from the active surface to an edge of the meniscus concave surface contacting the bump solder ball is about a 1/7 length of the maximum diameter of a respective bump solder ball at below or above a section of the bump solder ball having the maximum diameter. | 12-18-2008 |
| 20090045513 | SEMICONDUCTOR CHIP PACKAGE, ELECTRONIC DEVICE INCLUDING THE SEMICONDUCTOR CHIP PACKAGE AND METHODS OF FABRICATING THE ELECTRONIC DEVICE - A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other. | 02-19-2009 |
| 20090065919 | SEMICONDUCTOR PACKAGE HAVING RESIN SUBSTRATE WITH RECESS AND METHOD OF FABRICATING THE SAME - In one embodiment, a semiconductor package disclosed herein can be generally characterized as including a resin substrate having a first recess, a first interconnection disposed on a surface of the first recess, a first semiconductor chip disposed in the first recess, and an underfill resin layer substantially filling the first recess and covering a side surface of the first semiconductor chip. The first semiconductor chip is electrically connected to the first interconnection. | 03-12-2009 |
