Patent application number | Description | Published |
20100087066 | Selective Chemical Etch Method for MRAM Freelayers - An etching process is employed to selectively pattern an exposed magnetic layer of a magnetic thin film structure. The etching process includes exposing the magnetic layer to an etchant composition including at least one weakly absorbing acid, a surfactant inhibitor soluble in the at least one weakly absorbing acid, and at least one cation additive. The presence of the at least one cation additive increases dissolution inhibition of an underlying tunnel barrier layer (i.e., increases etch selectivity) and permits the use of more soluble surfactant inhibitors in the etchant composition. | 04-08-2010 |
20100252775 | METHOD FOR FORMING AN INDIUM CAP LAYER - An indium cap layer is formed by blanket depositing indium onto a surface of metallic interconnects separated by interlayer dielectric, and then selectively chemically etching the indium located on the interlayer dielectric leaving an indium cap layer. Etchants containing a strong acid are provided for selectively removing the indium. | 10-07-2010 |
20110048930 | SELECTIVE NANOTUBE GROWTH INSIDE VIAS USING AN ION BEAM - A method of selectively growing one or more carbon nano-tubes includes forming an insulating layer on a substrate, the insulating layer having a top surface; forming a via in the insulating layer; forming an active metal layer over the insulating layer, including sidewall and bottom surfaces of the via; and removing the active metal layer at portions of the top surface with an ion beam to enable the selective growth of one or more carbon nano-tubes inside the via. | 03-03-2011 |
20110049655 | PILLAR-BASED INTERCONNECTS FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY - A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact. | 03-03-2011 |
20120115251 | PROCESS FOR SELECTIVELY PATTERNING A MAGNETIC FILM STRUCTURE - Processes for selectively patterning a magnetic film structure generally include selectively etching an exposed portion of a freelayer disposed on a tunnel barrier layer by a wet process, which includes exposing the freelayer to an etchant solution comprising at least one acid and an organophosphorus acid inhibitor or salt thereof, stopping on the tunnel barrier layer. | 05-10-2012 |
20120217590 | Filling Narrow Openings Using Ion Beam Etch - Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening. Furthermore, the method includes performing a first angled etching process to at least partially remove the first layer of first fill material from above the semiconductor device by at least partially removing a first portion of the first layer proximate an inlet of the opening without removing a second portion of the first layer proximate the bottom of said opening, and forming a second layer of second fill material above the semiconductor device by forming the second layer inside the opening and above the first layer. | 08-30-2012 |
20120299136 | PILLAR-BASED INTERCONNECTS FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY - A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact. | 11-29-2012 |
20130106552 | INDUCTOR WITH MULTIPLE POLYMERIC LAYERS | 05-02-2013 |
20130176095 | INDUCTOR WITH LAMINATED YOKE - A thin film inductor having yokes, one or more of which is laminated, and one or more conductors passing between the yokes. The laminated yoke or yokes help reduce eddy currents and/or hysteresis losses. | 07-11-2013 |
20130314192 | INDUCTOR WITH STACKED CONDUCTORS - A thin film coupled inductor, a thin film spiral inductor, and a system that includes an electronic device and a power supply or power converter incorporating one or more such inductors. A thin film coupled inductor includes a wafer substrate; a bottom yoke comprising a magnetic material above the wafer substrate; a first insulating layer above the bottom yoke; a first conductor above the bottom yoke and separated therefrom by the first insulating layer; a second insulating layer above the first conductor; a second conductor above the second insulating layer; a third insulating layer above the second conductor; and a non-planar top yoke above the third insulating layer, the top yoke comprising a magnetic material. | 11-28-2013 |
20140190003 | INDUCTOR WITH LAMINATED YOKE - A method for forming a thin film inductor having yokes, one or more of which is laminated, and one or more conductors passing between the yokes. The laminated yoke or yokes help reduce eddy currents and/or hysteresis losses. | 07-10-2014 |
20140191361 | ELECTROLESS PLATING OF COBALT ALLOYS FOR ON CHIP INDUCTORS - A method for forming an on-chip magnetic structure includes forming a seed layer over a substrate of a semiconductor chip. The seed layer is patterned to provide a plating location. A cobalt based alloy is electrolessly plated at the plating location to form an inductive structure on the semiconductor chip. | 07-10-2014 |
20140191362 | ELECTROLESS PLATING OF COBALT ALLOYS FOR ON CHIP INDUCTORS - A method for forming an on-chip magnetic structure includes forming a seed layer over a substrate of a semiconductor chip. The seed layer is patterned to provide a plating location. A cobalt based alloy is electrolessly plated at the plating location to form an inductive structure on the semiconductor chip. | 07-10-2014 |
20140216939 | LAMINATING MAGNETIC CORES FOR ON-CHIP MAGNETIC DEVICES - A laminating structure includes a first magnetic layer, a second magnetic layer, a first spacer disposed between the first and second magnetic layers and a second spacer disposed on the second magnetic layer. | 08-07-2014 |
20140216943 | LAMINATING MAGNETIC CORES FOR ON-CHIP MAGNETIC DEVICES - A laminating structure includes a first magnetic layer, a second magnetic layer, a first spacer disposed between the first and second magnetic layers and a second spacer disposed on the second magnetic layer. | 08-07-2014 |
20140239443 | ELECTROLESS PLATED MATERIAL FORMED DIRECTLY ON METAL - A method for forming magnetic conductors includes forming a metal structure on a substrate. Plating surfaces are prepared on the metal structure for electroless plating by at least one of: masking surfaces of the metal structure to prevent electroless plating on masked surfaces and/or activating a surface of the metal structure. Magnetic material is electrolessly plated directly on the plating surfaces to form a metal and magnetic material structure. | 08-28-2014 |
20140264676 | FORMING MAGNETIC MICROELECTROMECHANICAL INDUCTIVE COMPONENTS - A micro-electromechanical device and method of manufacture are disclosed. A sacrificial layer is formed on a silicon substrate. A metal layer is formed on a top surface of the sacrificial layer. Soft magnetic material is electrolessly deposited on the metal layer to manufacture the micro-electromechanical device. The sacrificial layer is removed to produce a metal beam separated from the silicon substrate by a space. | 09-18-2014 |
20140273283 | FORMING MAGNETIC MICROELECTROMECHANICAL INDUCTIVE COMPONENTS - A micro-electromechanical device and method of manufacture are disclosed. A sacrificial layer is formed on a silicon substrate. A metal layer is formed on a top surface of the sacrificial layer. Soft magnetic material is electrolessly deposited on the metal layer to manufacture the micro-electromechanical device. The sacrificial layer is removed to produce a metal beam separated from the silicon substrate by a space. | 09-18-2014 |
20150061815 | PLANAR INDUCTORS WITH CLOSED MAGNETIC LOOPS - A planar closed-magnetic-loop inductor and a method of fabricating the inductor are described. The inductor includes a first material comprising a cross-sectional shape including at least four segments, at least one of the at least four segments including a first edge and a second edge on opposite sides of an axial line through the at least one of the at least four segments. The first edge and the second edge are not parallel. | 03-05-2015 |
20150064362 | PLANAR INDUCTORS WITH CLOSED MAGNETIC LOOPS - A planar closed-magnetic-loop inductor and a method of fabricating the inductor are described. The inductor includes a first material comprising a cross-sectional shape including at least four segments, at least one of the at least four segments including a first edge and a second edge on opposite sides of an axial line through the at least one of the at least four segments. The first edge and the second edge are not parallel. | 03-05-2015 |