| Patent application number | Description | Published |
|---|
| 20090114902 | TENSILE STRAINED GE FOR ELECTRONIC AND OPTOELECTRONIC APPLICATIONS - A semiconductor structure is provided. The semiconductor structure includes one or more III-IV material-based semiconductor layers. A tensile-strained Ge layer is formed on the one or more a III-IV material-based semiconductor layers. The tensile-strained Ge layer is produced through lattice-mismatched heteroepitaxy on the one or more a III-IV material-based semiconductor layers. | 05-07-2009 |
| 20090242935 | MONOLITHICALLY INTEGRATED PHOTODETECTORS - Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based photodetector comprising an active region including at least a portion of the monocrystalline silicon layer. The structure also includes a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region, wherein the second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon. The structure includes at least one non-silicon photodetector comprising an active region including at least a portion of the second monocrystalline semiconductor layer. | 10-01-2009 |
| 20100022073 | Method of Fabricating CMOS Inverter and Integrated Circuits Utilizing Strained Silicon Surface Channel MOSFETS - A method of fabricating a circuit comprising an nMOSFET includes providing a substrate, depositing a strain-inducing material comprising germanium over the substrate, and integrating a pMOSFET on the substrate, the pMOSFET comprising a strained channel having a surface roughness of less than 1 nm. The strain-inducing material is proximate to and in contact with the pMOSFET channel, the strain in the pMOSFET channel is induced by the strain-inducing material, and a source and a drain of the pMOSFET are at least partially formed in the strain-inducing material. | 01-28-2010 |
| 20100116329 | METHODS OF FORMING HIGH-EFFICIENCY SOLAR CELL STRUCTURES - Methods for forming solar cells include forming, over a substrate, a first junction comprising at least one III-V material and having a threading dislocation density of less than approximately 10 | 05-13-2010 |
| 20100116942 | HIGH-EFFICIENCY SOLAR CELL STRUCTURES - Solar cells include a substrate consisting essentially of silicon, a first junction disposed over the substrate, the first junction comprising at least one III-V material and having a threading dislocation density of less than approximately 10 | 05-13-2010 |
| 20100206216 | Method of Producing High Quality Relaxed Silicon Germanium Layers - A method for minimizing particle generation during deposition of a graded Si.sub.1-xGe.sub.x layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si.sub.1-xGe.sub.x layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm.sup.2 on the substrate. | 08-19-2010 |
| 20100221512 | DIGITAL METAMORPHIC ALLOYS FOR GRADED BUFFERS - Digital metamorphic alloy (DMA) buffer structures for transitioning from a bottom crystalline layer to a lattice mismatched top crystalline layer, and methods for manufacturing such layers are described. In some embodiments, a layered crystalline structure includes a first layer of a first crystalline material having a first in-plane lattice constant and a second layer of a second crystalline material disposed over the first layer and having a second in-plane lattice constant that is lattice mismatched with the first crystalline material. Multiple sets of buffer layers may be disposed between the first layer and the second layer. Each set is a digital metamorphic alloy including a buffer layer of a third crystalline material and a buffer layer of a fourth crystalline material where an effective in-plane lattice constant of each set falls between the first lattice of the first layer and the second lattice constant of the second layer. | 09-02-2010 |
| 20110073908 | III-V Semiconductor Device Structures - The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. | 03-31-2011 |
| 20110124146 | METHODS OF FORMING HIGH-EFFICIENCY MULTI-JUNCTION SOLAR CELL STRUCTURES - In various embodiments, solar cells include a junction including SiGe, a junction including at least one III-V material, and may be formed on silicon substrates and/or with silicon-based capping layers thereover. | 05-26-2011 |
| 20110132445 | HIGH-EFFICIENCY MULTI-JUNCTION SOLAR CELL STRUCTURES - In various embodiments, solar cells include a junction including SiGe, a junction including at least one III-V material, and may be formed on silicon substrates and/or with silicon-based capping layers thereover. | 06-09-2011 |
| 20110143495 | METHODS OF FORMING HIGH-EFFICIENCY MULTI-JUNCTION SOLAR CELL STRUCTURES - In various embodiments, solar cells include a junction including SiGe, a junction including at least one III-V material, and may be formed on silicon substrates and/or with silicon-based capping layers thereover. | 06-16-2011 |
