| Patent application number | Description | Published |
|---|
| 20080224729 | INTEGRATED CIRCUITS WITH REDUCED LEAKAGE CURRENT - In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential. | 09-18-2008 |
| 20080225568 | DENSE READ-ONLY MEMORY - In one embodiment, a read-only memory (ROM) is provided that includes: a plurality of word lines; a plurality of bit lines; a plurality of memory cell transistors arranged in rows corresponding to the word lines such that if a word line is asserted the corresponding memory cell transistors are conducting, the memory cell transistors also being arranged in columns corresponding to the bit lines; wherein each column of memory cell transistors is arranged into column groups, each column group including an access transistor coupled to the corresponding bit line, the remaining transistors in the column group being coupled in series from the access transistor to a last transistor in the column group, the last transistor in the column group being coupled to a voltage node. | 09-18-2008 |
| 20080225613 | MEMORY ROW AND COLUMN REDUNDANCY - In one embodiment, a memory includes a row and/or column redundancy architecture that uses binary cells to indicate whether a given row or column of memory cells is faulty. The binary cell is adapted to store a “repair true” signal in response to a conventional access to the corresponding row or column and also the assertion of a set signal. | 09-18-2008 |
| 20080259705 | HARDWARE AND SOFTWARE PROGRAMMABLE FUSES FOR MEMORY REPAIR - The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register. | 10-23-2008 |
| 20080266935 | DRAM STORAGE CAPACITOR WITHOUT A FIXED VOLTAGE REFERENCE - In one embodiment, a DRAM is provided that includes a plurality of memory cells, each memory cell including an access transistor and a storage capacitor, wherein the storage capacitor includes a first node coupled to the access transistor and a second node isolated from the first node, the second node comprising signal-bearing metal conductors. | 10-30-2008 |
| 20080266987 | DRAM WITH WORD LINE COMPENSATION - In one embodiment, a DRAM is provided that includes: a word line intersecting with a pair of bit lines, the DRAM including a memory cell at each intersection, each memory cell including an access transistor adapted to couple a storage cell to the corresponding bit line if its gate voltage is raised; and a word line compensation circuit adapted to compensate for a capacitively-coupled voltage increase on the corresponding bit line if the access transistor's gate voltage is raised. | 10-30-2008 |
| 20080266992 | DRAM WITH HYBRID SENSE AMPLIFIER - In one embodiment, a hybrid DRAM is provided that includes: a sense amplifier including a differential amplifier and regenerative latch, wherein the differential amplifier and regenerative latch are constructed using core transistors; and a plurality of memory cells coupled to the sense amplifier through a pair of bit lines, wherein the memory cells are constructed using I/O transistors. | 10-30-2008 |
| 20080291728 | Single-Poly Non-Volatile Memory Cell - A non-volatile memory cell is provided that includes: a substrate including diffusion regions for a read-out transistor; a capacitor formed in a poly-silicon layer adjacent the substrate, the capacitor including a floating gate for the read-out transistor and a control gate, the floating gate and the control gate each having finger extensions, the finger extensions from the floating gate interdigitating with the finger extensions from the control gate; and a programming line coupled to the control gate. | 11-27-2008 |
| 20090003113 | Block-by-Block Leakage Control and Interface - In one embodiment, a method of leakage control for a memory having an array of memory cells arranged into a plurality of sub-arrays is provided wherein each sub-array has a sleep mode of operation controlled by a sleep signal in which stored data is lost, and wherein each sub-array asserts a local clock if the sub-array is addressed. The method includes the act of asserting a sleep signal while addressing a given one of the sub-arrays such that only the given one of the sub-arrays is placed into the sleep mode. | 01-01-2009 |
| 20090010041 | Hybrid DRAM - In one embodiment, a hybrid DRAM is provided that includes: a sense amplifier including a differential amplifier and regenerative latch, wherein the differential amplifier and regenerative latch are constructed using core transistors that have a relatively thin gate oxide; and a plurality of memory cells coupled to the sense amplifier through a pair of bit lines, wherein each memory cell includes an access transistor coupled to a storage cell, the access transistor having a relatively thick gate oxide, whereby the storage capacitor is capable of being charged to a VIO power supply voltage that is greater than a VDD power supply voltage for the core transistors. | 01-08-2009 |
| 20090109766 | EFFICIENT SENSE COMMAND GENERATION - In one embodiment, a memory includes: an array of memory cells arranged according to word lines and columns, each column corresponding to bit lines; a sense amplifier adapted to couple to the bit lines to sense a binary content of selected cells from the array of memory cells, the sense amplifier sensing the binary content responsive to a sense command; an x-decoder configured to assert a selected one of the word lines in response to decoding an address as triggered by a clock edge, wherein the assertion of the selected word line switches on corresponding access transistors to develop voltages on the bit lines; and a bit line replica circuit adapted to replicate the development of the bit lines, the bit line replica circuit including a replica access transistor coupled between a replica bit line and a replica memory cell wherein the replica access transistor is switched on responsive to the clock edge such that the replica memory cell pulls the replica bit line to ground, the bit line replica circuit also including a comparator that asserts an output in response to comparing a voltage of the replica bit line to a threshold, the sense command being a buffered version of the output from the comparator. | 04-30-2009 |
| 20090109772 | RAM WITH INDEPENDENT LOCAL CLOCK - In one embodiment, a random access memory (RAM) is provided that includes: an array of memory cells arranged in rows corresponding to word lines, the memory cells also being arranged in columns corresponding to bit lines; a local clock source that asserts a local clock in response to an assertion of an external clock; a plurality of x-decoders, each x-decoder adapted to assert a corresponding one of the word lines in response to a decoding of an appropriate address, wherein the assertion of a word line couples a corresponding row of the memory cells to their bit lines such that the bit lines are developed with corresponding voltages; and a plurality of sense amplifiers adapted to sense the voltage developments of the bit lines so as to determine a binary content of the memory cells, wherein the local clock source is triggered to de-assert the local clock independently of whether the external clock has been de-asserted. | 04-30-2009 |
| 20090109778 | LOW-POWER SENSE AMPLIFIER - In one embodiment, a sense amplifier for sensing a binary state of a memory cell coupled to a bit line and a complementary bit line and for writing a binary state into the memory cell is provided. The sense amplifier includes: a first pair of switches including a first switch coupled to a node on the bit line and a second switch coupled to a node on the complementary bit line; a signal detector having a first input terminal coupled to the first switch and a second input terminal coupled to the second switch, the signal detector configured to sense voltages on the bit line and the complementary bit line through the first pair of switches during a read operation; a second pair of switches, wherein a first switch in the second pair couples between the node on the bit line and ground and is responsive to a data signal to be written to the memory cell and a second switch couples between the node on the complementary bit line and ground and is responsive to a complementary data signal to be written to the memory cell, wherein if either the data signal or the complementary data signal is true, a corresponding bit line is grounded so as to force the binary state of memory cell into an appropriate value during a write operation; and wherein the first pair of switches are controlled such that they turn on during a read operation while the signal detector determines the binary state of the memory cell, the first pair of switches being off during the write operation whereby a capacitance presented to the bit line and the complementary bit line by the sense amplifier is lower during the write operation than during the read operation. | 04-30-2009 |
| 20090109789 | DECODER WITH MEMORY - In one embodiment, a decoder for decoding an address having a plurality of bits ranging from a first address bit a | 04-30-2009 |
| 20090189685 | Leakage Control - In one embodiment, a leakage reduction circuit is provided that includes: a virtual power supply node; a first PMOS transistor coupled between the virtual power supply node and a power supply node; a second PMOS transistor having a source coupled to the power supply node; and a native NMOS transistor coupled between a drain of the second PMOS transistor and the virtual power supply node, the native NMOS transistor having a gate driven by the power supply node. | 07-30-2009 |
| 20090190389 | MULTI-PORT SRAM WITH SIX-TRANSISTOR MEMORY CELLS - In one embodiment, a multi-port SRAM is provided that comprises: a single input port and output port 6-T SRAM; and a multi-port control block circuit that includes: a plurality of input registers corresponding to a plurality of input ports to register corresponding input signals; an input multiplexer to select from the input registers to provide a selected input signal to the 6-T SRAM's single input port; a plurality of output registers corresponding to a plurality of output ports to register corresponding output signals; and an output de-multiplexer to select from the output registers to provide an output signal from the | 07-30-2009 |
| 20090190425 | SENSE AMPLIFIER READ LINE SHARING - A memory is provided that practices global read line sharing by including: a global read line, the memory being adapted to be pre-charge the global read line prior to a read operation; an I/O circuit to receive the global read line; and a plurality of sense amplifiers, each sense amplifier being multiplexed with respect to the global read line such that only a selected one of the sense amplifiers in the plurality is activated during a read operation to determine a bit decision, the memory being adapted to discharge the pre-charged global read line if the bit decision from the activated sense amplifier equals one, the pre-charged global read line thereby staying pre-charged if the bit decision from the activated sense amplifier equals zero. | 07-30-2009 |
| 20090316512 | BLOCK REDUNDANCY IMPLEMENTATION IN HEIRARCHICAL RAM'S - The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use. | 12-24-2009 |
| 20090322920 | Operational amplifier for an active pixel sensor - The present invention includes operational amplifier for an active pixel sensor that detects optical energy and generates an analog output that is proportional to the optical energy. The active pixel sensor operates in a number of different modes including: signal integration mode, the reset integration mode, column reset mode, and column signal readout mode. Each mode causes the operational amplifier to see a different output load. Accordingly, the operational amplifier includes a variable feedback circuit to provide compensation that provides sufficient amplifier stability for each operating mode of the active pixel sensor. For instance, the operational amplifier includes a bank of feedback capacitors, one or more of which are selected based on the operating mode to provide sufficient phase margin for stability, but also considering gain and bandwidth requirements of the operating mode. | 12-31-2009 |
| 20100185890 | SYNCHRONOUS GLOBAL CONTROLLER FOR ENHANCED PIPELINING - The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller. | 07-22-2010 |
| 20110141840 | NOR-OR DECODER - A decoder for decoding an address having a plurality of bits ranging from a first address bit a | 06-16-2011 |
