Patent application number | Description | Published |
20080230873 | SEMICONDUCTOR DEVICE WITH CAPACITOR AND/OR INDUCTOR AND METHOD OF MAKING - An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation. The device is coupled to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use. The device may be formed as one or more capacitors or as one or more inductors. Various structures may be used for the capacitor and the inductor. | 09-25-2008 |
20110001214 | SEMICONDUCTOR DEVICE WITH CAPACITOR AND/OR INDUCTOR AND METHOD OF MAKING - An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation. The device is coupled to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use. The device may be formed as one or more capacitors or as one or more inductors. Various structures may be used for the capacitor and the inductor. | 01-06-2011 |
20130055184 | METHOD AND SYSTEM FOR PHYSICAL VERIFICATION USING NETWORK SEGMENT CURRENT - A data processing system determines current information corresponding to a node included at a device design. Physical layout information corresponding to the node is received, the physical layout information including one or more layout geometries, the one or more layout geometries providing a circuit network. The circuit network may be partitioned into two or more network segments. A current conducted at a network segment is identified based on the current information. Information representative of dimensions and metal layer of a layout geometry included at the network segment is received. The computer determines that the current exceeds a predetermined maximum threshold, the predetermined maximum threshold determined based on the dimensions and metal layer. | 02-28-2013 |
20130320490 | INDUCTIVE ELEMENT WITH INTERRUPTER REGION AND METHOD FOR FORMING - A semiconductor device structure a semiconductor substrate having a first conductivity type and a top surface. A plurality of first doped regions is at a first depth below the top surface arranged in a checkerboard fashion. The first doped regions are of a second conductivity type. A dielectric layer is over the top surface. An inductive element is over the dielectric layer, wherein the inductive element is over the first doped regions. | 12-05-2013 |
20130326448 | Techniques for Electromigration Stress Determination in Interconnects of an Integrated Circuit - In one or more embodiments, one or more methods, processes, and/or systems described can determine stress failures in interconnect segments of integrated circuit designs and correct those failure via modifying the interconnect segments of the integrated circuit designs with one or more additions to the interconnect segments of the integrated circuit designs. Potentials can be received from a simulation, and one or more failures of an interconnect segment can be determined via the potentials from the simulation. For example, a failure can be determined via a comparison with a potential from the simulation and a critical potential. An interconnect segment can be modified with a stub such that a comparison with a potential from the simulation and a critical potential to provide a non-failing, modified interconnect segment. | 12-05-2013 |
20140258951 | Prioritized Design for Manufacturing Virtualization with Design Rule Checking Filtering - An approach is provided to generate a number of virtualized circuit designs by applying design-for-manufacturing (DFM) processes to a circuit design. The virtualized circuit designs are checked using design rule checks (DRCs), with the checking resulting in a design rule error quantity that corresponds to each of the virtualized circuit designs. One of the virtualized circuit designs is selected for use in manufacturing the circuit design with the selection based each of the design's design rule error quantities. | 09-11-2014 |
20140273391 | INDUCTIVE ELEMENT WITH INTERRUPTER REGION AND METHOD FOR FORMING - A semiconductor device structure a semiconductor substrate having a first conductivity type and a top surface. A plurality of first doped regions is at a first depth below the top surface arranged in a checkerboard fashion. The first doped regions are of a second conductivity type. A dielectric layer is over the top surface. An inductive element is over the dielectric layer, wherein the inductive element is over the first doped regions. | 09-18-2014 |
20150046893 | TECHNIQUES FOR ELECTROMIGRATION STRESS MITIGATION IN INTERCONNECTS OF AN INTEGRATED CIRCUIT DESIGN - A technique for electromigration stress mitigation in interconnects of an integrated circuit design includes generating a maximal spanning tree of a directed graph, which represents an interconnect network of an integrated circuit design. A first point on the spanning tree having a lowest stress and a second point on the spanning tree having a highest stress are located. A maximum first stress between the first and second points is determined. In response to determining the maximum first stress between the first and second points is greater than a critical stress, a stub is added to the spanning tree at a node between the first and second points. The maximum first stress between the first and second points is re-determined subsequent to adding the stub. | 02-12-2015 |
20150178438 | SEMICONDUCTOR MANUFACTURING USING DESIGN VERIFICATION WITH MARKERS - A first circuit design is entered in an electronic design automation (EDA) computer system. The first circuit design includes a first feature with a first node. A marker is associated with the first node and represents a voltage associated with the first node as an algebraic expression of a numerical value representing a property of the circuit design. The marker is used to determine if the component of the circuit design violates a design rule. | 06-25-2015 |
Patent application number | Description | Published |
20160100414 | SUPERPOSED SIGNALING FOR BANDWIDTH EFFICIENCY - Systems, methods and instrumentalities are disclosed for superposed signaling for bandwidth efficiency in wireless communications. Homogeneous and heterogeneous signals may be superposed on the same channel. Superposed signals may comprise, for example, multi carrier, frequency division and code division signals, including multiple access, e.g., OFDMA and CDMA, signals. Data for various receivers may be dynamically selected for signal superpositioning, for example, based on radio access technology, communication rate (e.g. high and low rates), distance between transmitter and receiver (e.g. near and far signals). Communication rate and power may be allocated to superposed signals. Interference nulling may be applied, for example, by selecting or excluding spreading codes and/or subcarriers. Nulled locations may be used to transmit critical information. Interference shaping may be applied to modify interference, e.g., by transmitting interference symbols using reserved spreading codes. Support information, e.g., code indices, code length and/or subcarriers, may be signaled to support or optimize performance. | 04-07-2016 |
Patent application number | Description | Published |
20100094512 | METHOD FOR CONTROLLING THE AUTOMATIC START/STOP SYSTEM OF THE THERMAL ENGINE OF A VEHICLE, CORRESPONDING SYSTEM AND USE THEREOF - A method implemented in a vehicle, using information representative of an operational state of the vehicle being provided by sensors and a data communication bus. The information is representative of the engagement and disengagement of an exploitation assistance brake (EAB) and a speed of the vehicle and of a pressure on a brake pedal of the vehicle. A cut-off condition (C | 04-15-2010 |
20100231152 | TRIPHASE ROTATING ELECTRIC MACHINE - A triphase rotating electric machine includes three coils evenly distributed around a rotational axes of the machine, and at least one first sensor, capable of generating a periodic signal to represent the position of the machine around the axle and a control circuit capable of controlling, when in the first mode, the conduction of a switch (KUH), linked to at least one of the three coils based on the periodic signal generated by the first sensor (U), such that the conduction phases of the switch (KUH) have a duration in the order of half the signal period (U). The control circuit is capable of controlling the switch (KUH), based on a second mode in which the conduction phases of the switch (KUH) have a duration in the order of a third of the signal period (U). | 09-16-2010 |
20100298088 | MICRO-HYBRID SYSTEM FOR MOTOR VEHICLE INCORPORATING A PILOTING STRATEGIES MODULE - The micro-hybrid system for a transport vehicle comprises a rotary electric machine ( | 11-25-2010 |
20110232597 | METHOD AND DEVICE FOR CONTROLLING AN ENGINE STOP/RESTART SYSTEM TO BE MOUNTED ON AN AUTOMOBILE - A method and a device ( | 09-29-2011 |