| Patent application number | Description | Published |
|---|
| 20090065898 | INTEGRATED BEOL THIN FILM RESISTOR - In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers. | 03-12-2009 |
| 20090270017 | Slurryless Mechanical Planarization for Substrate Reclamation - A patterned portion of a patterned semiconductor substrate is removed by abrasive mechanical planarization employing an abrasive pad but without employing any slurry. Preferably, water is supplied to enhance the removal rate during the mechanical planarization. The removal rate of material is substantially independent for common materials employed in back-end-of-line (BEOL) semiconductor materials, which enables non-selective removal of the material containing metallization structures. The removal rate of silicon is lower than the removal rate for the BEOL semiconductor materials, enabling a self-stopping planarization process. | 10-29-2009 |
| 20100127395 | METHODS FOR SELECTIVE REVERSE MASK PLANARIZATION AND INTERCONNECT STRUCTURES FORMED THEREBY - Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer. | 05-27-2010 |
| 20100248479 | CMP METHOD - The instant invention is a method of polishing a substrate including contacting a substrate having at least one metal layer including copper with a chemical-mechanical polishing composition. The CMP composition includes an abrasive, a surfactant, an oxidizer, an organic acid including polyacrylic acid or polymethacrylic acid, a corrosion inhibitor, and a liquid carrier. A portion of the copper in the metal layer is abraded to polish the substrate. A second CMP composition contacts the abraded substrate, the second acrylate free composition including an abrasive, a surfactant, an oxidizer, and a corrosion inhibitor, and a liquid carrier. Any dendrites that may have formed on the substrate are removed through abrasion. | 09-30-2010 |
| 20100327219 | SOLUTION FOR FORMING POLISHING SLURRY, POLISHING SLURRY AND RELATED METHODS - A solution for forming a polishing slurry, the polishing slurry and related methods are disclosed. The solution for forming a polishing slurry may include 1H-benzotriazole (BTA) dissolved in an ionic surfactant such as a sodium alkyl sulfate solution, and perhaps a polyacrylic acid (PAA) solution. The solution can be filtered and used in a polishing slurry. This approach to solubilizing BTA results in a high BTA concentration in a polishing slurry without addition of foreign components to the slurry or increased safety hazard. In addition, the solution is easier to ship because it is very stable (e.g., can be frozen and thawed) and has less volume compared to conventional approaches. Further, the polishing slurry performance is vastly improved due to the removal of particles that can cause scratching. | 12-30-2010 |
| 20110127635 | Integrated BEOL Thin Film Resistor - In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers. | 06-02-2011 |
| 20110315527 | PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process. | 12-29-2011 |
| 20110316097 | PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a wiring layer and substrate. The method further includes forming an insulator layer over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity of the MEMS. | 12-29-2011 |
