| Patent application number | Description | Published |
|---|
| 20080258740 | SELF-CALIBRATING DRIVER - A self-calibration system includes a variable current source to generate a default source current for charging a capacitive load, and a load charge calibrator to detect a voltage associated with the capacitive load when charged by the default source current, and to generate a current control feedback according to the detected voltage and a desired charged voltage of the capacitive load, the current control feedback to indicate to the variable current source a charge current capable of charging the capacitive load to the desired charged voltage. | 10-23-2008 |
| 20080258797 | NON-RESISTIVE LOAD DRIVER - Embodiments of the invention relate to a method and apparatus to drive non-resistive loads. The non-resistive load driver may include two or more drivers, such as a high-drive circuit and a low-drive circuit, to drive rail-to-rail output voltages and to stabilize the output voltages at a substantially constant level. The high-drive circuit may drive the output voltage of the non-resistive load driver to a threshold level, whereas the low-drive circuit may modify the output voltage of the non-resistive load driver to approximate an input voltage of the non-resistive load driver, and compensate any leakage associated with the non-resistive loads to provide a substantially constant output voltage. The low-drive circuit consumes less current than the high-drive circuit. The non-resistive load driver consumes less power and use less chip space. Alternatively, the non-resistive load driver may be implemented using a single driver with multiple modes, such as a low-drive mode and a high-drive mode, by changing a bias current of the non-resistive load driver between a high current mode and a low current mode. | 10-23-2008 |
| 20080259017 | REDUCING POWER CONSUMPTION IN A LIQUID CRYSTAL DISPLAY - Embodiments of the invention relate to a method and apparatus to reduce power consumption in a passive matrix LCD driver circuit by using a plurality of drive buffers and active power management of sub-blocks in the passive matrix LCD drive circuit. Each drive buffer may operate in a first phase, which may include a high-drive mode to drive an LCD voltage to a threshold voltage level and a low-drive mode to modify the LCD voltage to approximate an input voltage of the drive buffer, and to maintain a constant LCD voltage level. The low-drive buffer consumes less current than the high-drive buffer, thus reducing power consumption. The drive buffer may also operate in a second phase, also a no-drive mode, in which the drive buffer and the bias voltage generator may be completely turned off, to further reduce power consumption. The drive buffer may be used to drive capacitive loads, as well as partially-resistive loads and inductive loads. | 10-23-2008 |
| 20080259065 | CONFIGURABLE LIQUID CRYSTAL DISPLAY DRIVER SYSTEM - Embodiments of the invention relate to a configurable LCD driver system having a plurality of configurable LCD drivers. Each LCD driver may be configured as a common or segment driver by selecting a drive voltage from an appropriate set of drive voltages associated with a common or segment driver in accordance with certain parameters, such as whether a user may configure the LCD driver as a common driver or segment driver, a multiplex ratio, and/or bias ratio of an LCD panel. The drive time and drive strength associated with the LCD driver may also be configurable. The selected drive voltage may be provided to a drive buffer to output an LCD drive voltage waveform for driving one or more segments or pixels in an LCD panel. A memory may store appropriate display data for both the segment and common drivers to control the output drive capability of the LCD driver. | 10-23-2008 |
| Patent application number | Description | Published |
|---|
| 20100117707 | CLAMP CONTROL CIRCUIT HAVING CURRENT FEEDBACK - In accordance with an aspect of the present invention, an external FET driving circuit includes a driving portion, a drain-to-gate clamp portion and a current feedback portion. The driving portion provides a driving signal to the external FET. The drain-to-gate clamp portion protects the external FET from flyback current, when the external FET is quickly turned OFF. The current feedback portion controls the driving signal provided by the driver. | 05-13-2010 |
| 20100156384 | METHODS AND APPARATUS FOR HIGHER-ORDER CORRECTION OF A BANDGAP VOLTAGE REFERENCE - Methods and apparatus for higher-order correction of bandgap voltage references are disclosed. An example bandgap voltage reference circuit disclosed herein comprises a bandgap voltage generation circuit comprising a first resistor, the bandgap voltage generation circuit configured to generate a proportional-to-absolute-temperature current to drive the first resistor to produce a first voltage, the first voltage contributing to an output bandgap voltage, and a first correction circuit electrically coupled to the first resistor and configured to provide a first correction current, the first correction circuit comprising a first nonlinear device configured to generate the first correction current only within a first temperature range, the first correction current decreasing with increasing temperature, the first correction current to drive the first resistor to increase the first voltage only within the first temperature range. | 06-24-2010 |
| 20100259235 | Voltage Regulator with Quasi Floating Gate Pass Element - Various apparatuses, methods and systems for a voltage regulator are disclosed herein. For example, some embodiments provide an apparatus for regulating a voltage including an N-channel transistor that is connected between an input and an output, an error amplifier that is connected to the output, a capacitor that is connected between the error amplifier and a gate of the N-channel transistor, and a comparator that is connected to a node between the error amplifier and the capacitor. The apparatus also includes a charge pump that is switchably connected to the gate of the N-channel transistor. The apparatus is adapted to connect the charge pump to the gate of the N-channel transistor when a voltage at the node between the error amplifier and the capacitor rises above a threshold voltage. | 10-14-2010 |
