| Patent application number | Description | Published |
|---|
| 20080240421 | Method and apparatus for advanced encryption standard (AES) block cipher - The speed at which encrypt and decrypt operations may be performed in a general purpose processor is increased by providing a separate encrypt data path and decrypt data path. With separate data paths, each of the data paths may be individually optimized in order to reduce delays in a critical path. In addition, delays may be hidden in a non-critical last round. | 10-02-2008 |
| 20080240422 | Efficient advanced encryption standard (AES) Datapath using hybrid rijndael S-Box - The speed at which an AES decrypt operation may be performed in a general purpose processor is increased by providing a separate decrypt data path. The critical path delay of the aes decrypt path is reduced by combining multiply and inverse operations in the Inverse SubBytes transformation. A further decrease in critical path delay in the aes decrypt data path is provided by merging appropriate constants of the inverse mix-column transform into a map function. | 10-02-2008 |
| 20080304659 | METHOD AND APPARATUS FOR EXPANSION KEY GENERATION FOR BLOCK CIPHERS - A key scheduler performs a key-expansion to generate round keys for AES encryption and decryption just-in-time for each AES round. The key scheduler pre-computes slow operations in a current clock cycle to reduce the critical delay path for computing the round key for a next AES round. | 12-11-2008 |
| 20090003593 | UNIFIED SYSTEM ARCHITECTURE FOR ELLIPTIC-CURVE CRYTPOGRAPHY - A system for performing public key encryption is provided. The system supports mathematical operations for a plurality of public key encryption algorithms such as Rivert, Shamir, Aldeman (RSA) and Diffie-Hellman key exchange (DH) and Elliptic Curve Cryptosystem (ECC). The system supports both prime fields and different composite binary fields. | 01-01-2009 |
| 20090003594 | MODULUS SCALING FOR ELLIPTIC-CURVE CRYPTOGRAPHY - Modulus scaling applied a reduction techniques decreases time to perform modular arithmetic operations by avoiding shifting and multiplication operations. Modulus scaling may be applied to both integer and binary fields and the scaling multiplier factor is chosen based on a selected reduction technique for the modular arithmetic operation. | 01-01-2009 |
| 20090003595 | SCALE-INVARIANT BARRETT REDUCTION FOR ELLIPTIC-CURVE CYRPTOGRAPHY - The computation time to perform scalar point multiplication in an Elliptic Curve Group is reduced by modifying the Barrett Reduction technique. Computations are performed using an N-bit scaled modulus based a modulus m having k-bits to provide a scaled result, with N being greater than k. The N-bit scaled result is reduced to a k-bit result using a pre-computed N-bit scaled reduction parameter in an optimal manner avoiding shifting/aligning operations for any arbitrary values of k, N. | 01-01-2009 |
| 20090003596 | EFFICIENT ELLIPTIC-CURVE CRYPTOGRAPHY BASED ON PRIMALITY OF THE ORDER OF THE ECC-GROUP - Time to perform scalar point multiplication used for ECC is reduced by minimizing the number of shifting operations. These operations are minimized by applying modulus scaling by performing selective comparisons of points at intermediate computations based on primality of the order of an ECC group. | 01-01-2009 |
| 20090006511 | POLYNOMIAL-BASIS TO NORMAL-BASIS TRANSFORMATION FOR BINARY GALOIS-FIELDS GF(2m) - Basis conversion from polynomial-basis form to normal-basis form is provided for both generic polynomials and special irreducible polynomials in the form of “all ones”, referred to as “all-ones-polynomials” (AOP). Generation and storing of large matrices is minimized by creating matrices on the fly, or by providing an alternate means of computing a result with minimal hardware extensions. | 01-01-2009 |
| 20090006512 | NORMAL-BASIS TO CANONICAL-BASIS TRANSFORMATION FOR BINARY GALOIS-FIELDS GF(2m) - Basis conversion from normal form to canonical form is provided for both generic polynomials and special irreducible polynomials in the form of “all ones”, referred to as “all-ones-polynomials” (AOP). Generation and storing of large matrices is minimized by creating matrices on the fly, or by providing an alternate means of computing a result with minimal hardware extensions. | 01-01-2009 |
| 20090006517 | UNIFIED INTEGER/GALOIS FIELD (2m) MULTIPLIER ARCHITECTURE FOR ELLIPTIC-CURVE CRYTPOGRAPHY - A unified integer/Galois-Field 2 | 01-01-2009 |
| 20090089617 | METHOD AND APPARATUS FOR TESTING MATHEMATICAL ALGORITHMS - A method and apparatus for testing mathematical programs where code coverage is exceedingly difficult to hit with random data test vectors (probability <2 | 04-02-2009 |
| 20090158132 | Determining a message residue - In one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect, circuitry to access at least a portion of a first number having a first endian format, determine a second number based on a bit reflection and shift of a third number having an endian format opposite to that of the first endian format, and perform a polynomial multiplication of the first number and the at least a portion of the first number. | 06-18-2009 |
| 20090164546 | METHOD AND APPARATUS FOR EFFICIENT PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) - A method and apparatus to optimize each of the plurality of reduction stages in a Cyclic Redundancy Check (CRC) circuit to produce a residue for a block of data decreases area used to perform the reduction while maintaining the same delay through the plurality of stages of the reduction logic. A hybrid mix of Karatsuba algorithm, classical multiplications and serial division in various stages in the CRC reduction circuit results in about a twenty percent reduction in area on the average with no decrease in critical path delay. | 06-25-2009 |
| 20100153829 | RESIDUE GENERATION - In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value. | 06-17-2010 |
| 20110106872 | Method and apparatus for providing an area-efficient large unsigned integer multiplier - An area efficient multiplier having high performance at modest clock speeds is presented. The performance of the multiplier is based on optimal choice of a number of levels of Karatsuba decomposition. The multiplier may be used to perform efficient modular reduction of large numbers greater than the size of the multiplier. | 05-05-2011 |
