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Erdem
Erdem Arkun, San Carlos, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120104443 | IIIOxNy ON SINGLE CRYSTAL SOI SUBSTRATE AND III n GROWTH PLATFORM - A silicon-on-insulator (SOI) substrate structure and method of fabrication including a single crystal silicon substrate, a layer of single crystal rare earth oxide formed on the substrate, a layer of engineered single crystal silicon formed on the layer of single crystal rare earth oxide, and a single crystal insulator layer of IIIO | 05-03-2012 |
| 20120104567 | IIIOxNy ON REO/Si - An insulative layer on a semiconductor substrate and a method of fabricating the structure includes the steps of depositing a single crystal layer of rare earth oxide on a semiconductor substrate to provide electrical insulation and thermal management. The rare earth oxide is crystal lattice matched to the substrate. A layer of single crystal IIIO | 05-03-2012 |
Erdem Bedri, Midland, MI US
| Patent application number | Description | Published |
|---|---|---|
| 20090012230 | Sealant Composition - The instant invention is a sealant composition comprising an ultra-high solid polyurethane dispersion comprising. The ultra-high solid polyurethane dispersion comprises (1) a first component comprising a first polyurethane prepolymer or a first polyurethane prepolymer emulsion, (2) a second component comprising a media phase selected from the group consisting of a second polyurethane prepolymer emulsion, a low solid content polyurethane dispersion, a seed latex, and combinations thereof; and (3) a chain extender. The ultra-high solid polyurethane dispersion has at least a solid content of at least 65 percent by weight of solid content, based on the total weight of the ultra-high solid polyurethane dispersion, and a viscosity of less than 5000 cps at 20 rpm at 21° C. using spindle #4 with Brookfield viscometer. The sealant composition may further include optionally one or more surfactants, optionally one or more dispersants, optionally one or more thickeners, optionally one or more pigments, optionally one or more fillers, optionally one or more freeze-thaw agent, optionally one or more neutralizing agents, optionally one or more plasticizers, and/or combinations thereof. | 01-08-2009 |
Erdem Bircan, Redwood City, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080239609 | METHOD AND APPARATUS PROVIDING FINAL TEST AND TRIMMING FOR A POWER SUPPLY CONTROLLER - A power supply controller having final test and trim circuitry. In one embodiment, a power supply controller for switched mode power supply includes a selector circuit, a trim circuit, a shutdown circuit and a disable circuit. The trim circuit includes a programmable circuit connection that can be selected by the selector circuit by toggling a voltage on an external terminal such as for example a power supply terminal, a control terminal or a function terminal of the power supply controller. The programmable circuit connection in the trim circuit can be programmed by applying a programming voltage to the external terminal. The shutdown circuit shuts down the power supply controller if the temperature rises above an over temperature threshold voltage. The shutdown circuit includes adjustment circuitry that can be used to test the shutdown circuit. The adjustment circuitry can adjust and reduce the over temperature threshold of the power supply controller. Thus, the power supply controller can be tested without having to actually heat the part. The disable circuit includes a programmable circuit connection, which when programmed prevents further trimming of power supply controller and prevents adjustment of the shutdown circuit over temperature threshold. | 10-02-2008 |
Erdem Catak, Katy, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20120037361 | ARRANGEMENT AND METHOD FOR DETECTING FLUID INFLUX AND/OR LOSS IN A WELL BORE - An arrangement and method for more accurately detecting well bore fluid kicks and/or losses by coupling a fluid flow measurement device to a substantially vertical tubular, such as a bell nipple or marine riser, to more accurately determine the flow rate of fluid flowing out of the well bore. Well bore fluid kicks and/or fluid losses are preferably detected by comparing the determined flow rate of fluid flowing out of the well bore and the flow rate of fluid injected into the well bore for any difference indicative of a well bore fluid kick or loss event. | 02-16-2012 |
Erdem Hokenek, Yorktown Heights, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090276432 | DATA FILE STORING MULTIPLE DATA TYPES WITH CONTROLLED DATA ACCESS - A method and apparatus for efficiently storing multiple data types in a computer's register or data file. A single data file can store data with a variety of sizes and number formats, including integers, fractions, and mixed numbers. The register file is partitioned into fields, such that only the relevant portions of the register file are read or written. | 11-05-2009 |
| 20100122068 | MULTITHREADED PROCESSOR WITH MULTIPLE CONCURRENT PIPELINES PER THREAD - A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines. | 05-13-2010 |
| 20100199073 | MULTITHREADED PROCESSOR WITH MULTIPLE CONCURRENT PIPELINES PER THREAD - A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines. | 08-05-2010 |
| 20100199075 | MULTITHREADED PROCESSOR WITH MULTIPLE CONCURRENT PIPELINES PER THREAD - A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines. | 08-05-2010 |
| 20120096243 | MULTITHREADED PROCESSOR WITH MULTIPLE CONCURRENT PIPELINES PER THREAD - A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines. | 04-19-2012 |
Erdem Kaltalioglu, Wappingers Falls, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080213993 | Method and Apparatus of Stress Relief in Semiconductor Structures - A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer. | 09-04-2008 |
Erdem Kaltalioglu, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080290459 | MIM Capacitors - A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate. | 11-27-2008 |
Erdem Korkmaz, Istanbul TR
| Patent application number | Description | Published |
|---|---|---|
| 20090113925 | REFRIGERATOR - The present invention relates to a refrigerator ( | 05-07-2009 |
Erdem Koseomur, New South Wales AU
| Patent application number | Description | Published |
|---|---|---|
| 20080196594 | Doner Kebab Slicing Robot - The Doner Kebab Slicing Robot comprises of two linear slide assemblies preferably made of metal. The linear slides consist of track plate and wheel plate components. The vertical slide assembly contains a blade head ( | 08-21-2008 |
Erdem Tuzun, Houston, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110104156 | Methods and materials for treating autoimmune and/or complement mediated diseases and conditions - Disclosed are methods for treating an autoimmune and/or complement mediated disease or condition in a subject. The methods include administering to the subject a compound which inhibits the subject's classical complement pathway. The methods include administering to the subject a compound which inhibits the subject's classical complement pathway. Compositions which include inhibitors of C1q, C1r, C1s, C2 or C4 and a pharmaceutically acceptable excipient are also described. | 05-05-2011 |
Erdem Ultanir, San Carlos, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090075179 | EXTREME ULTRAVIOLET (EUV) MASK PROTECTION AGAINST INSPECTION LASER DAMAGE - Extreme Ultraviolet (EUV) mask protection against laser inspection damage is generally described. In one example, a photomask includes a substrate, a bilayer stack coupled with the substrate, the bilayer stack including about 30-50 bilayers wherein the bilayers include alternating films of a first material and a second material, a protective film including polycrystalline carbon coupled with the bilayer stack to protect the bilayer stack against laser inspection damage, and a capping film coupled with the protective film. | 03-19-2009 |
Erdem Usul, Istanbul TR
| Patent application number | Description | Published |
|---|---|---|
| 20110265019 | SOCIAL GROUPS SYSTEM AND METHOD - A system and method for the creation of a virtual world on top of an online community are provided. The system for the creation of a virtual world on top of an online community may be known as SROUPS. SROUPS creates or provides a tool for online community users to create virtual worlds on top of any online community. | 10-27-2011 |